9.5.2 I²C Protocol

Input voltage – Logic levels for I²C SDA and SCL terminals are not fixed. For the TPS56X20, a logic “0” (LOW) should be 0V and a logic “1” (HIGH) can be any voltage between 1.8V and 3.3V. Logic HIGH is generated by external pullup resistors (see next paragraph).

Output voltage – the I²C bus has external pullup resistors, one for SCL and one for SDA. These pull up to a voltage called VDD which must lie between 1.8V and 3.3V. The outputs are pulled down to their logic LOW levels by open-drain outputs and pulled up to their logic HIGH levels by these external pullups. The pullups must be selected so that the current into any chip when pulled LOW by that chip’s open drain output (=VDD/RPULLUP) is less than 3.3mA.

Data format – One clock pulse on the SCL clock line is generated for each bit of data to be transferred. The data on the SDA line must be stable during the HIGH period of the SCL clock line. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW.

START and STOP conditions – A HIGH to LOW transition on the SDA line while the SCL line is HIGH defines a START condition. A LOW to HIGH transition on the SDA line while the SCL line is HIGH defines a STOP condition. START and STOP conditions are always generated by the Master. The bus is considered to be BUSY after the condition. It is considered to be free again after a minimum of 4.7µS after the STOP condition.

The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. START and repeated START are functionally identical.

Every byte of data out on the SDA line is 8 bits long. 9 clocks occur for each byte (the additional clock being for an ACK signal put onto the bus by the TPS56X20 pulling down on the bus to acknowledge receipt of the data). In the following diagrams, shaded blocks indicate SDA data generated by the TPS56X20 being sent to the Master I²C controller, while white blocks indicate SDA data generated by the Master being received by the TPS56X20. The Master always generates the SCL signal.

Sending data to the TPS56X20 is accomplished using the following 3-byte sequence, referred to as a Write Byte transaction as follows:

Figure 29. A complete Write Byte transfer, adapted from SMBUS spec

Reading back data from the TPS56X20 is accomplished using the following 4-byte sequence, referred to as a Read Byte transaction:

Figure 30. A complete Read Byte transfer, adapted from SMBUS spec

On the TPS56X20, the I2C bus is inactive until:

1. Both SDA and SCL have been at a logic high simultaneously to prevent power sequencing issues
2. VREG5 is in regulation.

Control registers should not be written to during the Soft Start time, but can be written before VOUT is enabled or after the PGOOD terminal or status register go high, indicating that soft start is complete.

Until a VOUT command has been accepted, the TPS56X20’s output voltage will be determined by the external resistor divider feedback to the VFB terminals, the condition of the EN terminals, and the capacitance on the SS terminals.

When the TPS56X20 receives a Chip Address code it recognizes to be its own, it will respond by sending an ACK (pulling down on the SDA bus during the next clock on the SCL bus). If the address is not recognized, the TPS56X20 assumes that the I²C message is intended for another chip on the bus, and it takes no action. It will disregard data sent thereafter until the next START is begun.

If, after recognizing its Chip Address, the TPS56X20 receives a valid Register Address, it will send an ACK and prepare to receive a Data Byte to be sent to that Register.

If a valid Data Byte is then received, it will send an ACK and will set the output voltage to the desired value. If the byte is deemed invalid, ACK will not be sent and the Master will need to retry by sending a STOP sequence followed by a new START sequence and an initiating resend of the entire address/data packet. When sending data to the Output Voltage register, the output voltage will only change upon receipt of a valid data byte.