JAJSEQ9E November   2013  – December 2017 TPS56520 , TPS56720 , TPS56920 , TPS56C20

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション回路
  4. 4 改訂履歴
  5. 5 概要(続き)
  6. 6 List of Devices
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
    2.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 PWM Operation
      2. 9.3.2 PWM Frequency and Adaptive On-Time Control
      3. 9.3.3 VIN and Power VIN Terminals (VIN and PVIN)
      4. 9.3.4 Auto-Skip Eco-mode™ Control
      5. 9.3.5 Soft Start and Pre-Biased Soft Start
      6. 9.3.6 Power Good
      7. 9.3.7 Overcurrent Protection
      8. 9.3.8 UVLO Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation at Light Loads
    5. 9.5 Programming
      1. 9.5.1 I2C Interface
      2. 9.5.2 I2C Protocol
      3. 9.5.3 I2C Chip Address Byte
    6. 9.6 Register Maps
      1. 9.6.1 I2C Register Address Byte
      2. 9.6.2 Output Voltage Registers
      3. 9.6.3 CheckSum Bit (VOUT Register Only)
      4. 9.6.4 Control Registers
      5. 9.6.5 Latchoff
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 TPS56520, TPS56720 and TPS56920, 5-A, 7-A, and 9-A Converter
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Output Voltage Resistors Selection
            1. 10.2.1.2.1.1 Output Filter Selection
          2. 10.2.1.2.2 Input Capacitor Selection
          3. 10.2.1.2.3 Bootstrap Capacitor Selection
          4. 10.2.1.2.4 VREG5 Capacitor Selection
      2. 10.2.2 TPS56520, TPS56720 and TPS56920 Application Performance Curves
      3. 10.2.3 TPS56C20 12-A Converter
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Design Procedure
        3. 10.2.3.3 TPS56C20 Application Performance Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 開発サポート
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 関連リンク
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PWP|24
サーマルパッド・メカニカル・データ
発注情報

8.6 Timing Requirements

MIN TYP MAX UNIT
SOFT START
Issc SS charge current VSS=0.5V , 25 °C –6.4 –6 –5.6  µA
IssD SS discharge current VSS=0.5V 0.14 0.2  0.26 mA
SERIAL INTERFACE(1)(2)(3)
VIL LOW level input voltage 0.6 V
VIH HIGH level input voltage 1.8 V
Vhys Hysteresis of Schmitt trigger inputs 0.11 V
VOL LOW level output voltage (Open drain, 3mA sink current) 0.4 V
tSP Pulse width of spikes suppressed by input filter 32 ns
fscl SCL clock frequency 400 kHz
tHD;STA Hold time (repeated) START condition. 0.6 us
tLOW LOW period of SCL clock 1.3 us
tHIGH HIGH period of SCL clock 0.6 us
tSU;STA Set-up time for a repeated START condition 0.6 us
tHD;DAT Data Hold time 50 900 ns
tSU;DAT Data set-up time 100 ns
tr Rise time (SDA or SCL) 20+0.1Cb(4) 300 ns
tf Fall time (SDA or SCL) 20+0.1Cb(4) 300 ns
tSU;STO Set-up time for STOP condition 0.6 us
tBUF Bus free time between STOP and START condition 1.3 us
Cb Capacitive load for each bus line 400 pF
(1) Ensured by design. Not production tested.
(2) Refer to Figure 1 below for I2C Timing Definitions
(3) Cb = capacitance of bus line in pF
TPS56C20 TPS56920 TPS56720 TPS56520 I2C_timing_SLVSCB6.gifFigure 1. I2C Timing Definitions (reproduced from Phillips I2C spec Version 1.1)