JAJSBL0E November   2011  – May 2017 TPS62170 , TPS62171 , TPS62172 , TPS62173

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Voltage Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable and Shutdown (EN)
      2. 8.3.2 Current Limit and Short Circuit Protection
      3. 8.3.3 Power Good (PG)
      4. 8.3.4 Undervoltage Lockout (UVLO)
      5. 8.3.5 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Soft Start
      2. 8.4.2 Pulse Width Modulation (PWM) Operation
      3. 8.4.3 Power Save Mode Operation
      4. 8.4.4 100% Duty-Cycle Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design with WEBENCH® Tools
        2. 9.2.2.2 Programming the Output Voltage
        3. 9.2.2.3 External Component Selection
          1. 9.2.2.3.1 Inductor Selection
        4. 9.2.2.4 Capacitor Selection
          1. 9.2.2.4.1 Output Capacitor
          2. 9.2.2.4.2 Input Capacitor
        5. 9.2.2.5 Output Filter and Loop Stability
        6. 9.2.2.6 TPS6216x Components List
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Inverting Power Supply
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
        1. 12.1.2.1 WEBENCH®ツールによるカスタム設計
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連リンク
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
Pin voltage range(2) VIN –0.3 20 V
EN, SW (DC) –0.3 VIN+ 0.3 V
SW (AC), less than 10ns(3) –2 24.5
FB, PG, VOS –0.3 7 V
Power good sink current PG 10 mA
Operating junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to network ground terminal.
(3) While switching.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
Supply Voltage, VIN 3 17 V
Output Voltage, VOUT 0.9 6 V
Operating junction temperature, TJ –40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) TPS6217x UNIT
DSG (WSON)
8 PINS
RθJA Junction-to-ambient thermal resistance 61.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 61.3 °C/W
RθJB Junction-to-board thermal resistance 15.5 °C/W
ψJT Junction-to-top characterization parameter 0.4 °C/W
ψJB Junction-to-board characterization parameter 15.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

Over junction temperature range (TJ = –40°C to +125°C), typical values at VIN = 12 V and TJ = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
VIN Input voltage range(1) 3 17 V
IQ Operating quiescent current EN = High, IOUT = 0 mA, device not switching 17 30 µA
TJ = -40°C to +85°C 17 25
ISD Shutdown current(2) EN = Low 1.5 25 µA
TJ = -40°C to +85°C 1.5 4
VUVLO Undervoltage lockout threshold Falling input voltage 2.6 2.7 2.82 V
Hysteresis 180 mV
TSD Thermal shutdown temperature rising temperature 160 °C
Thermal shutdown hysteresis falling temperature 20
CONTROL (EN, PG)
VEN_H High level input threshold voltage (EN) 0.9 0.6 V
VEN_L Low level input threshold voltage (EN) 0.56 0.3 V
ILKG_EN Input leakage current (EN) EN = VIN or GND 0.01 1 µA
VTH_PG Power good threshold voltage Rising (%VOUT) 92% 95% 98%
Falling (%VOUT) 87% 90% 93%
VOL_PG Power good output low voltage IPG = –2 mA 0.07 0.3 V
ILKG_PG Input leakage current (PG) VPG = 1.8 V 1 400 nA
POWER SWITCH
RDS(ON) High-side MOSFET ON-resistance VIN ≥ 6 V 300 600 mΩ
VIN= 3 V 430
Low-side MOSFET ON-resistance VIN≥ 6 V 120 200 mΩ
VIN = 3 V 165
ILIMF High-side MOSFET forward current limit(3) VIN = 12 V, TJ= 25°C 0.85 1.05 1.35 A
OUTPUT
VREF Internal reference voltage(4) 0.8 V
ILKG_FB Pin leakage current (FB) TPS62170, VFB= 1.2 V 5 400 nA
VOUT Output voltage range (TPS62170) VIN ≥ VOUT 0.9 6.0 V
Initial output voltage accuracy(5) PWM mode operation, VIN ≥ VOUT + 1 V –3% 3%
Power save mode operation, COUT= 22 µF -3.5% 4%
DC output voltage load regulation VIN = 12 V, VOUT = 3.3 V, PWM mode operation 0.05 %/A
DC output voltage line regulation 3 V ≤ VIN ≤ 17 V, VOUT = 3.3 V, IOUT = 0.5 A, PWM mode operation 0.02 %/V
(1) The device is still functional down to under voltage lockout (see parameter VUVLO).
(2) Current into VIN pin.
(3) This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Current Limit and Short Circuit Protection).
(4) This is the voltage regulated at the FB pin.
(5) This is the accuracy provided by the device itself (line and load regulation effects are not included). For fixed voltage versions, the (internal) resistive feedback divider is included.

7.6 Typical Characteristics

TPS62170 TPS62171 TPS62172 TPS62173 SLVSAT8_IQ.gif
Figure 1. Quiescent Current
TPS62170 TPS62171 TPS62172 TPS62173 SLVSAT8_RDSonHS.png
Figure 3. High-Side Switch
TPS62170 TPS62171 TPS62172 TPS62173 SLVSAT8_ISD.gif
Figure 2. Shutdown Current
TPS62170 TPS62171 TPS62172 TPS62173 SLVSAT8_RDSonLS.png
Figure 4. Low-Side Switch