JAJSBL0E November   2011  – May 2017 TPS62170 , TPS62171 , TPS62172 , TPS62173

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Voltage Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable and Shutdown (EN)
      2. 8.3.2 Current Limit and Short Circuit Protection
      3. 8.3.3 Power Good (PG)
      4. 8.3.4 Undervoltage Lockout (UVLO)
      5. 8.3.5 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Soft Start
      2. 8.4.2 Pulse Width Modulation (PWM) Operation
      3. 8.4.3 Power Save Mode Operation
      4. 8.4.4 100% Duty-Cycle Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design with WEBENCH® Tools
        2. 9.2.2.2 Programming the Output Voltage
        3. 9.2.2.3 External Component Selection
          1. 9.2.2.3.1 Inductor Selection
        4. 9.2.2.4 Capacitor Selection
          1. 9.2.2.4.1 Output Capacitor
          2. 9.2.2.4.2 Input Capacitor
        5. 9.2.2.5 Output Filter and Loop Stability
        6. 9.2.2.6 TPS6216x Components List
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Inverting Power Supply
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
        1. 12.1.2.1 WEBENCH®ツールによるカスタム設計
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連リンク
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Detailed Description

8.1 Overview

The TPS6217x synchronous step-down DC-DC converters are based on DCS-Control™ (Direct Control with Seamless transition into power save mode), an advanced regulation topology, that combines the advantages of hysteretic, voltage mode and current mode control including an AC loop directly associated to the output voltage. This control loop takes information about output voltage changes and feeds it directly to a fast comparator stage. It sets the switching frequency, which is constant for steady state operating conditions, and provides immediate response to dynamic load changes. To get accurate DC load regulation, a voltage feedback loop is used. The internally compensated regulation network achieves fast and stable operation with small external components and low ESR capacitors.

The DCS-Control™ topology supports pulse width modulation (PWM) mode for medium and heavy load conditions and a power save mode at light loads. During PWM mode, it operates at its nominal switching frequency in continuous conduction mode. This frequency is typically about 2.25 MHz with a controlled frequency variation depending on the input voltage. If the load current decreases, the converter enters power save mode to sustain high efficiency down to very light loads. In power save mode, the switching frequency decreases linearly with the load current. Since DCS-Control™ supports both operation modes within one single building block, the transition from PWM to power save mode is seamless without effects on the output voltage.

Fixed output voltage versions provide smallest solution size and lowest current consumption, requiring only 3 external components. An internal current limit supports nominal output currents of up to 500 mA.

The TPS6217x family offers both excellent DC voltage and superior load transient regulation, combined with very low output voltage ripple, minimizing interference with RF circuits.

8.2 Functional Block Diagram

TPS62170 TPS62171 TPS62172 TPS62173 SLVSAT8_FBDadj.gif Figure 5. TPS62170 (Adjustable Output Voltage)
TPS62170 TPS62171 TPS62172 TPS62173 SLVSAT8_FBDfix.gif Figure 6. TPS62171/TPS62172/TPS62173 (Fixed Output Voltage)

8.3 Feature Description

8.3.1 Enable and Shutdown (EN)

When enable (EN) is set high, the device starts operation.

Shutdown is forced if EN is pulled low with a shutdown current of typically 1.5 µA. During shutdown, the internal power MOSFETs as well as the entire control circuitry are turned off. The internal resistive divider pulls down the output voltage smoothly. If the EN pin is low, an internal pull-down resistor of about 400 kΩ is connected and keeps it low, to avoid bouncing.

Connecting the EN pin to an appropriate output signal of another power rail provides sequencing of multiple power rails.

8.3.2 Current Limit and Short Circuit Protection

The TPS6217x devices are protected against heavy load and short circuit events. At heavy loads, the current limit determines the maximum output current. If the current limit is reached, the high-side FET is turned off. Avoiding shoot-through current, the low-side FET is switched on to allow the inductor current to decrease. The high-side FET turns on again, only if the current in the low-side FET decreases below the low-side current limit threshold of typically 0.7A.

The output current of the device is limited by the current limit (see Electrical Characteristics). Due to internal propagation delay, the actual current can exceed the static current limit during that time. The dynamic current limit is calculated as follows:

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Equation 1. TPS62170 TPS62171 TPS62172 TPS62173 SLVSAG7_eqilim.gif

where

  • ILIMF is the static current limit, specified in Electrical Characteristics
  • L is the inductor value
  • VL is the voltage across the inductor
  • tPD is the internal propagation delay

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The dynamic high-side switch peak current is calculated as follows:

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Equation 2. TPS62170 TPS62171 TPS62172 TPS62173 SLVSAT8_eqilimdyn.gif

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Take care with the current limit, if the input voltage is high and very small inductances are used.

8.3.3 Power Good (PG)

The TPS6217x has a built in power good (PG) function to indicate whether the output voltage has reached its appropriate level or not. The PG signal can be used for startup sequencing of multiple rails. The PG pin is an open-drain output that requires a pull-up resistor (to any voltage below 7 V). It can sink 2 mA of current and maintain its specified logic low level. It is high impedance when the device is turned off due to EN, UVLO or thermal shutdown. If not used, the PG pin should be connected to GND but may be left floating.

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Table 1. Power Good Pin Logic Table

Device State PG Logic Status
High Impedance Low
Enable (EN=High) VFB ≥ VTH_PG √
VFB ≤ VTH_PG √
Shutdown (EN=Low) √
UVLO 0.7 V < VIN < VUVLO √
Thermal Shutdown TJ > TSD √
Power Supply Removal VIN < 0.7 V √

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8.3.4 Undervoltage Lockout (UVLO)

If the input voltage drops, the under voltage lockout prevents misoperation of the device by switching off both the power FETs. The under voltage lockout threshold is set typically to 2.7 V. The device is fully operational for voltages above the UVLO threshold and turns off if the input voltage trips the threshold. The converter starts operation again once the input voltage exceeds the threshold by a hysteresis of typically 180 mV.

8.3.5 Thermal Shutdown

The junction temperature (Tj) of the device is monitored by an internal temperature sensor. If Tj exceeds 160°C (typical), the device goes into thermal shut down. Both the high-side and low-side power FETs are turned off and PG goes high impedance. When Tj decreases below the hysteresis amount, the converter resumes normal operation, beginning with soft start. To avoid unstable conditions, a hysteresis of typically 20°C is implemented on the thermal shut down temperature.

8.4 Device Functional Modes

8.4.1 Soft Start

The internal soft start circuitry controls the output voltage slope during startup. This avoids excessive inrush current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from high-impedance power sources or batteries. When EN is set to start device operation, the device starts switching after a delay of about 50 µs and VOUT rises with a slope of about 25 mV/µs. See Figure 30 and Figure 31 for typical startup operation.

The TPS6217x can start into a pre-biased output. During monotonic pre-biased startup, the low-side MOSFET is not allowed to turn on until the device's internal ramp sets an output voltage above the pre-bias voltage.

8.4.2 Pulse Width Modulation (PWM) Operation

The TPS6217x operates with pulse width modulation in continuous conduction mode (CCM) with a nominal switching frequency of about 2.25 MHz. The frequency variation in PWM is controlled and depends on VIN, VOUT and the inductance. The device operates in PWM mode as long the output current is higher than half the inductor's ripple current. To maintain high efficiency at light loads, the device enters power save mode at the boundary to discontinuous conduction mode (DCM). This happens if the output current becomes smaller than half the inductor's ripple current.

8.4.3 Power Save Mode Operation

The TPS6217x's built in power save mode is entered seamlessly, if the load current decreases. This secures a high efficiency in light load operation. The device remains in power save mode as long as the inductor current is discontinuous.

In power save mode the switching frequency decreases linearly with the load current maintaining high efficiency. The transition into and out of power save mode happens within the entire regulation scheme and is seamless in both directions.

TPS6217x includes a fixed on-time circuitry. This on-time, in steady-state operation, is estimated as:

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Equation 3. TPS62170 TPS62171 TPS62172 TPS62173 SLVSAT8_eqton.gif

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For very small output voltages, the on-time increases beyond the result of Equation 3, to stay above an absolute minimum on-time, tON(min), which is around 80 ns, to limit switching losses. The peak inductor current in PSM is approximated by:

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Equation 4. TPS62170 TPS62171 TPS62172 TPS62173 SLVSAG7_eqilpfm.gif

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When VIN decreases to typically 15% above VOUT, the TPS6217x does not enter power save mode, regardless of the load current. The device maintains output regulation in PWM mode.

8.4.4 100% Duty-Cycle Operation

The duty cycle of the buck converter is given by D = VOUT/VIN and increases as the input voltage comes close to the output voltage. In this case, the device starts 100% duty cycle operation turning on the high-side switch 100% of the time. The high-side switch stays turned on as long as the output voltage is below the internal setpoint. This allows the conversion of small input to output voltage differences, such as for the longest operation time of battery-powered applications. In 100% duty cycle mode, the low-side FET is switched off.

The minimum input voltage to maintain output voltage regulation, depending on the load current and the output voltage level, is calculated as:

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Equation 5. TPS62170 TPS62171 TPS62172 TPS62173 SLVSAG7_eqvinmin.gif

where

  • IOUT is the output current
  • RDS(on) is the RDS(on) of the high-side FET
  • RL is the DC resistance of the inductor used