JAJSLH2 March   2021 TPS62810M , TPS62811M , TPS62812M , TPS62813M

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Schematic
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Precise Enable
      2. 9.3.2 COMP/FSET
      3. 9.3.3 MODE/SYNC
      4. 9.3.4 Spread Spectrum Clocking (SSC)
      5. 9.3.5 Undervoltage Lockout (UVLO)
      6. 9.3.6 Power Good Output (PG)
      7. 9.3.7 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Pulse Width Modulation (PWM) Operation
      2. 9.4.2 Power Save Mode Operation (PWM/PFM)
      3. 9.4.3 100% Duty-Cycle Operation
      4. 9.4.4 Current Limit and Short Circuit Protection
      5. 9.4.5 Foldback Current Limit and Short Circuit Protection
      6. 9.4.6 Output Discharge
      7. 9.4.7 Soft Start/Tracking (SS/TR)
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Programming the Output Voltage
      2. 10.1.2 Inductor Selection
      3. 10.1.3 Capacitor Selection
        1. 10.1.3.1 Input Capacitor
        2. 10.1.3.2 Output Capacitor
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Voltage Tracking
      2. 10.3.2 Synchronizing to an External Clock
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 用語集
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

over operating junction temperature (TJ = –55°C to +150°C) and VIN = 2.75 V to 6 V. Typical values at VIN = 5 V and TJ = 25°C. (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Operating quiescent current EN = high, IOUT = 0 mA, device not switching,
TJ = 125°C		 21 µA
IQ Operating quiescent current EN = high, IOUT = 0 mA, device not switching 15 30 µA
ISD Shutdown current EN = 0 V, at TJ = 125 °C 18 µA
ISD Shutdown current EN = 0 V, nominal value at TJ = 25 °C,
max value at TJ = 150°C		 1.5 26 µA
VUVLO Undervoltage lockout threshold Rising input voltage 2.5 2.6 2.75 V
Falling input voltage 2.25 2.5 2.6 V
TSD Thermal shutdown temperature Rising junction temperature 170 °C
Thermal shutdown hysteresis 15
CONTROL (EN, SS/TR, PG, MODE)
VIH High level input voltage for MODE pin 1.1 V
VIL Low level input voltage for MODE pin 0.3 V
fSYNC Frequency range on MODE pin for synchronization Requires a resistor from COMP/FSET to GND, see the Application and Implementation section 1.8 4 MHz
Duty cycle of synchronization signal at MODE pin 40% 50% 60%
Time to lock to external frequency 50 µs
VIH Input threshold voltage for EN pin; rising edge 1.06 1.1 1.15 V
VIL Input threshold voltage for EN pin; falling edge 0.96 1.0 1.05 V
ILKG Input leakage current for EN, MODE/SYNC VIH = VIN or VIL = GND 150 nA
Resistance from COMP/FSET to GND for logic low Internal frequency setting with f = 2.25 MHz 0 2.5 kΩ
Voltage on COMP/FSET for logic high Internal frequency setting with f = 2.25 MHz VIN V
VTH_PG UVP power good threshold voltage; dc level Rising (%VFB) 92% 95% 98%
UVP power good threshold voltage; dc level Falling (%VFB) 87% 90% 93%
OVP power good threshold; dc level Rising (%VFB) 107% 110% 113%
OVP power good threshold; dc level Falling (%VFB) 104% 107% 111%
Power good de-glitch time For a high level to low level transition on power good 40 µs
VOL_PG Power good output low voltage IPG = 2 mA 0.07 0.3 V
ILKG_PG Input leakage current (PG) VPG = 5 V 100 nA
ISS/TR SS/TR pin source current 2.1 2.5 2.8 µA
Tracking gain VFB/VSS/TR 1
Tracking offset Feedback voltage with VSS/TR = 0 V 17 mV
POWER SWITCH
RDS(ON) High-side MOSFET ON-resistance VIN ≥ 5 V 37 60 mΩ
RDS(ON) Low-side MOSFET ON-resistance VIN ≥ 5 V 15 35 mΩ
High-side MOSFET leakage current VIN = 6 V; V(SW) = 0 V 30 µA
Low-side MOSFET leakage current V(SW) = 6 V 55 µA
SW leakage V(SW) = 0.6 V; current into SW pin –0.025 30 µA
ILIMH High-side MOSFET current limit DC value, for TPS62810; VIN = 3 V to 6 V 4.8 5.6 6.65 A
ILIMH High-side MOSFET current limit DC value, for TPS62813; VIN = 3 V to 6 V 3.9 4.5 5.35 A
ILIMH High-side MOSFET current limit DC value, for TPS62812; VIN = 3 V to 6 V 2.8 3.4 4.3 A
ILIMH High-side MOSFET current limit DC value, for TPS62811; VIN = 3 V to 6 V 2.0 2.6 3.35 A
ILIMNEG Negative valley current limit DC value –1.8 A
fS PWM switching frequency range 1.8 2.25 4 MHz
fS PWM switching frequency
                 		 With COMP/FSET tied to VIN or GND 2.025 2.25 2.475 MHz
PWM switching frequency tolerance Using a resistor from COMP/FSET to GND, fs = 1.8 MHz to 4 MHz –19% 18%
ton,min Minimum on time of HS FET TJ = –40°C to 125°C, VIN = 3.3 V 50 75 ns
ton,min Minimum on time of LS FET VIN = 3.3 V 30 ns
OUTPUT
VFB Feedback voltage 0.6 V
ILKG_FB Input leakage current (FB) VFB = 0.6 V 1 70 nA
VFB Feedback voltage accuracy VIN ≥ VOUT + 1 V PWM mode –1% 1%
VIN ≥ VOUT + 1 V;
VOUT ≥ 1.5 V		 PFM mode;
Co,eff ≥ 22 µF,
L = 0.47 µH		 –1% 2%
1 V ≤ VOUT < 1.5 V PFM mode;
Co,eff ≥ 47 µF,
L = 0.47 µH		 –1% 2.5%
VFB Feedback voltage accuracy with voltage tracking VIN ≥ VOUT + 1 V;
VSS/TR = 0.3 V		 PWM mode –1% 7%
Load regulation  PWM mode operation 0.05 %/A
Line regulation PWM mode operation, IOUT = 1 A, VIN ≥ VOUT + 1 V 0.02 %/V
Output discharge resistance 50 Ω
tdelay Start-up delay time IOUT = 0 mA, time from EN = high to start switching; VIN applied already 135 250 650 µs
tramp Ramp time; SS/TR pin open IOUT = 0 mA, time from first switching pulse until 95% of nominal output voltage; device not in current limit 100 150 200 µs