JAJSLM0 March   2021 TPS62865 , TPS62867

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Save Mode
      2. 8.3.2 Forced PWM Mode
      3. 8.3.3 100% Duty Cycle Mode Operation
      4. 8.3.4 Soft Start
      5. 8.3.5 Switch Current Limit and HICCUP Short-Circuit Protection
      6. 8.3.6 Undervoltage Lockout
      7. 8.3.7 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable and Disable (EN)
      2. 8.4.2 Power Good (PG)
      3. 8.4.3 Voltage Setting and Mode Selection (VSET/MODE)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Setting The Output Voltage
        3. 9.2.2.3 Output Filter Design
        4. 9.2.2.4 Inductor Selection
        5. 9.2.2.5 Capacitor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.4 Soft Start

After enabling the device, there is a 700-µs (typical) enable delay (tdelay) before the device starts switching. After the enable delay, an internal soft start-up circuitry ramps up the output voltage with a period of 1 ms (tRamp). This avoids excessive inrush current and creates a smooth output voltage rise-slope. It also prevents excessive voltage drops of primary cells and rechargeable batteries with high internal impedance. The device is able to start into a pre-biased output capacitor. It starts with the applied bias voltage and ramps the output voltage to its nominal value.

GUID-D2309AAC-3179-4B05-911A-ED9B3B7CE5F9-low.gifFigure 8-1 Start-up Sequence