JAJSJC9B September   2020  – July 2021 TPS62868 , TPS62869

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C InterfaceTiming Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Save Mode
      2. 8.3.2 Forced PWM Mode
      3. 8.3.3 100% Duty Cycle Mode Operation
      4. 8.3.4 Start-up
      5. 8.3.5 Switch Current Limit and HICCUP Short-Circuit Protection
      6. 8.3.6 Undervoltage Lockout (UVLO)
      7. 8.3.7 Thermal Warning and Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable and Disable (EN)
      2. 8.4.2 Output Discharge
      3. 8.4.3 Start-Up Output Voltage and I2C Target Address Selection
        1. 8.4.3.1 TPS6286xxA Devices
        2. 8.4.3.2 TPS6286xxxC Devices
      4. 8.4.4 Select Output Voltage Registers (VID)
      5. 8.4.5 Power Good ( PG)
    5. 8.5 Programming
      1. 8.5.1 Serial Interface Description
      2. 8.5.2 Standard-, Fast-, and Fast-Mode Plus Protocol
      3. 8.5.3 HS-Mode Protocol
      4. 8.5.4 I2C Update Sequence
      5. 8.5.5 I2C Register Reset
    6. 8.6 Register Map
      1. 8.6.1 Target Address Byte
      2. 8.6.2 Register Address Byte
      3. 8.6.3 VOUT Register 1
      4. 8.6.4 VOUT Register 2
      5. 8.6.5 CONTROL Register
      6. 8.6.6 STATUS Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Setting The Output Voltage
        2. 9.2.2.2 Output Filter Design
        3. 9.2.2.3 Inductor Selection
        4. 9.2.2.4 Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application – TPS6286x0A and TPS6286x0xC Devices
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
        1. 9.3.2.1 Setting the Output Voltage
        2. 9.3.2.2 Output Filter Design
        3. 9.3.2.3 Inductor Selection
        4. 9.3.2.4 Capacitor Selection
      3. 9.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 サポート・リソース
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Trademarks
    6. 12.6 Glossary
    7. 12.7 Electrostatic Discharge Caution
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

TJ = -40 °C to 125 °C, and VIN = 2.4 V to 5.5 V. Typical values are at TJ = 25 °C and VIN = 5 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Quiescent current TPS6286x1A/C,
TPS6286x2A/C		 EN = High, no load, device not switching 4 10 µA
TPS6286x0A/C 9 15
IQ_VOS Operating quiescent current into VOS pin EN = High, no load, device not switching,
VVOS = 1.8 V 		18 µA
ISD
Shutdown current

 EN = Low, TJ = –40°C to 85°C
 0.24 1 µA
VUVLO Undervoltage lockout threshold VIN rising 2.2 2.3 2.4 V
VIN falling 2.1 2.2 2.3 V
TJW Thermal warning threshold TJ rising 130 °C
Thermal warning hysteresis TJ falling 20 °C
TJSD Thermal shutdown threshold TJ rising 150 °C

Thermal shutdown hysteresis

 TJ falling 20 °C
LOGIC INTERFACE EN, SDA, SCL
VIH
High-level input threshold voltage at EN, SCL, SDA, VSET/VID

 0.84 V
VIL Low-level input threshold voltage at EN, SCL, SDA, VSET/VID 0.4 V
ISCL,LKG Input leakage current into SCL pin 0.01 0.8 µA
ISDA,LKG Input leakage current into SDA pin 0.01 0.1 µA
IEN,LKG Input leakage current into EN pin 0.01 0.1 µA
CSCL Parasitic capacitance at SCL 1 pF
CSDA Parasitic capacitance at SDA 2.4 pF
STARTUP, POWER GOOD
tDelay Enable delay time TPS6286xA Time from EN high to device starts switching, R1 = 249kΩ 420 700 1100 µs
TPS6286x0C Time from EN high to device starts switching 100 350 900
tRamp Output voltage ramp time Time from device starts switching to power good 0.85 1 1.5 ms
VPG Power good lower threshold(1) VVOS referenced to VOUT nominal  85 91 96 %
Power good upper threshold VVOS referenced to VOUT nominal  103 111 120 %
tPG,DLY Power good deglitch delay Rising and falling edges 34 µs
OUTPUT
VOUT
Output voltage accuracy

 FPWM, no Load, TJ = 0℃ to 85℃ -1 1 %
FPWM, no Load -2 2 %
IVOS,LKG
Input leakage current into VOS pin

 EN = Low, Output discharge disabled, VVOS = 1.8 V, TPS6286x1A/C 0.2 2.5 µA
RDIS
Output discharge resistor at VOS pin

 3.5 Ω
Load regulation VOUT = 0.9 V, FPWM  0.04 %/A
POWER SWITCH
RDS(on) High-side FET on-resistance 11 mΩ
Low-side FET on-resistance 10.5 mΩ
ILIM High-side FET forward current limit TPS62868 5 5.5 6 A
TPS62869 7 7.7 8.5 A
Low-side FET forward current limit TPS62868 4.5 A
TPS62869 6.5 A
Low-side FET negative current limit TPS62868, TPS62869 -3 A
fSW PWM switching frequency IOUT = 1 A, VOUT = 0.9 V 2.4 MHz
(1) TPS6286x0A and TPS6286x00C device variants do not have a lower PG threshold. In these device variants the PG signal is high if the start-up ramp is complete and the output voltage is below the upper PG threshold.