JAJSMG2 November   2023 TPS6287B10 , TPS6287B25

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed-Frequency DCS-Control Topology
      2. 8.3.2  Forced-PWM and Power-Save Modes
      3. 8.3.3  Transient Non-Synchronous Mode (optional)
      4. 8.3.4  Precise Enable
      5. 8.3.5  Start-Up
      6. 8.3.6  Output Voltage Setting
        1. 8.3.6.1 Output Voltage Range
        2. 8.3.6.2 Output Voltage Setpoint
        3. 8.3.6.3 Non-Default Output Voltage Setpoint
        4. 8.3.6.4 Dynamic Voltage Scaling
        5. 8.3.6.5 Droop Compensation
      7. 8.3.7  Compensation (COMP)
      8. 8.3.8  Mode Selection / Clock Synchronization (MODE/SYNC)
      9. 8.3.9  Spread Spectrum Clocking (SSC)
      10. 8.3.10 Output Discharge
      11. 8.3.11 Undervoltage Lockout (UVLO)
      12. 8.3.12 Overvoltage Lockout (OVLO)
      13. 8.3.13 Overcurrent Protection
        1. 8.3.13.1 Cycle-by-Cycle Current Limiting
        2. 8.3.13.2 Hiccup Mode
        3. 8.3.13.3 Current-Limit Mode
      14. 8.3.14 Power Good (PG)
        1. 8.3.14.1 Standalone / Primary Device Behavior
        2. 8.3.14.2 Secondary Device Behavior
      15. 8.3.15 Remote Sense
      16. 8.3.16 Thermal Warning and Shutdown
      17. 8.3.17 Stacked Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset
      2. 8.4.2 Undervoltage Lockout
      3. 8.4.3 Standby
      4. 8.4.4 On
    5. 8.5 Programming
      1. 8.5.1 Serial Interface Description
      2. 8.5.2 Standard-, Fast-, Fast-Mode Plus Protocol
      3. 8.5.3 HS-Mode Protocol
      4. 8.5.4 I2C Update Sequence
      5. 8.5.5 I2C Register Reset
      6. 8.5.6 Dynamic Voltage Scaling (DVS)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Selecting the Input Capacitors
        3. 9.2.2.3 Selecting the Compensation Resistor
        4. 9.2.2.4 Selecting the Output Capacitors
        5. 9.2.2.5 Selecting the Compensation Capacitor CC
        6. 9.2.2.6 Selecting the Compensation Capacitor CC2
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application - TPS6287BxV Devices
      1. 9.3.1 Design Requirements for TPS6287BxV
    4. 9.4 Typical Application Using Two TPS6287B25 in a Stacked Configuration
      1. 9.4.1 Design Requirements For Two Stacked Devices
      2. 9.4.2 Detailed Design Procedure
        1. 9.4.2.1 Selecting the Compensation Resistor
        2. 9.4.2.2 Selecting the Output Capacitors
        3. 9.4.2.3 Selecting the Compensation Capacitor CC
      3. 9.4.3 Application Curves for Two Stacked Devices
    5. 9.5 Typical Application Using Three TPS6287B25 in a Stacked Configuration
      1. 9.5.1 Application Curves
    6. 9.6 Power Supply Recommendations
    7. 9.7 Layout
      1. 9.7.1 Layout Guidelines
      2. 9.7.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Device Registers
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-20230126-SS0I-JKFP-HNJ6-WMTRCHB2GRWR-low.svg Figure 5-1 RZV Package 24 Pin VQFN
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
1 VOSNS

I

 Output voltage sense (differential output voltage sensing).
2 EN I This pin is the enable pin of the device. Connect to this pin using a series resistor of at least 15 kΩ. A logic low level on this pin disables the device, and a logic high level on the pin enables the device. Do not leave this pin unconnected.

For stacked operation interconnect EN pins of all stacked devices with a resistor to the supply voltage or a GPIO of a processor. See Section 8.3.17 for a detailed description.
3 VSET1 I Start-up output voltage set pin. A resistor or short-circuit to GND or VIN defines the selected output voltage. See Table 8-4
4 VSET2 I Start-up output voltage set pin. A resistor or short-circuit to GND or VIN defines the selected output voltage. See Table 8-4
5, 6, 15, 16 VIN P Power supply input. Connect the input capacitor as close as possible between pin VIN and GND.
7, 8,

13, 14

 GND GND Ground pin
9, 10, 11, 12 SW O This pin is the switch pin of the converter and is connected to the internal Power MOSFETs.
17 SYNCOUT O Internal clock output pin for synchronization in stacked mode. Leave this pin floating for single device operation. Connect this pin to the MODE/SYNC pin of the next device in the daisy-chain in stacked operation. Do not use this pin to connect to a non-TPS6287Bx- device.

During start-up, this pin is used to identify if a device must operate as a secondary converter in stacked operation. Connect a 47-kΩ resistor from this pin to GND to define a secondary converter in stacked operation. See Section 8.3.17 for a detailed description.
18 MODE/SYNC I The device runs in Power-Save mode when this pin is pulled low. If the pin is pulled high, the device runs in Forced-PWM mode. Do not leave this pin unconnected. The mode pin can also be used to synchronize the device to an external clock.

19

VSET4

I

 Start-up output voltage set pin. A logic low level or a logic high level on the pin defines the start-up output voltage according to Table 8-6

19

SDA

I/O

 I2C serial data pin. Do not leave this pin floating. Connect a pullup to logic high level.

Connect to GND for secondary devices in stacked operation.

20

VSET3

 I Start-up output voltage set pin. A logic low level or a logic high level on the pin defines the start-up output voltage according to Table 8-6

20

 SCL I/O I2C serial clock pin. Do not leave this pin floating. Connect a pullup resistor to a logic high level.

Connect to GND for secondary devices in stacked operation.

21

 PG I/O Open drain power-good output. Low impedance when not "power good", high impedance when "power good". This pin can be left open or be tied to GND when not used in single device operation.

In stacked operation interconnect the PG pins of all stacked devices. Only the PG pin of the primary converter in stacked operation is an open drain output. For devices that are defined as secondary converters in stacked mode the pin is an input pin. See Section 8.3.17 for a detailed description.

22

 AGND GND Analog Ground. Connect to GND.

23

 COMP — Device compensation input. A resistor and capacitor from this pin to AGND define the compensation of the control loop.

In stacked operation connect the COMP pins of all stacked devices together and connect a resistor and capacitor between the common COMP node and AGND.

24

GOSNS

—

 Output ground sense (differential output voltage sensing)

Exposed Thermal Pads

 — The thermal pads must be soldered to GND to achieve an appropriate thermal resistance and for mechanical stability.
(1) I = input, O = output, P = power, GND = ground