6.2.2.1.1 Controller With External Feedback Resistor

For BUCK1, the voltage can be set using external feedback resistor. For all other bucks, the voltage is set by the default OTP settings and no resistor divider is required. For BUCK1, The internal voltage reference is set to 0.4 V.The output voltage is set with a resistor divider from the output node to the FB pin. TI recommends using a 1% tolerance or better to get accurate number. Use Equation 1 to calculate the value of R2.

To set the output voltage to 5 V, use a value of 294 kΩ for R1 and 25.5 kΩ for R2.

Figure 6-4 Controller Diagram With External Feedback Resistor

6.2.2.1.2 Selecting the Inductor

Placement of an inductor is required between the external FETs and the output capacitors. Together, the inductor and output capacitors make the double-pole that contributes to stability. Additionally, the inductor is directly responsible for the output ripple, efficiency, and transient performance. As the inductance used increases, the ripple current decreases, which typically results in increased efficiency. However, as the inductance used increases, the transient performance decreases. Finally, the inductor selected must be rated for appropriate saturation current, core losses, and DC resistance (DCR).

Use Equation 2 to calculate the recommended inductance for the controller.

Equation 2.

where

• V_OUT is the typical output voltage.
• V_IN is the typical input voltage.
• f_SW is the typical switching frequency.
• I_OUT(MAX) is the maximum load current.
• K_IND is the ratio of I_Lripple to the I_OUT(MAX). For this application, TI recommends that K_IND is set to a value from 0.2 to 0.4.

With the chosen inductance value, the peak current for the inductor in steady state operation, I_L(MAX), can be calculated using Equation 3. The rated saturation current of the inductor must be higher than the I_L(MAX) current.

Equation 3.

6.2.2.1.3 Selecting the Output Capacitors

TI recommends using ceramic capacitors with low ESR values to provide the lowest output voltage ripple. The output capacitor requires an X7R or an X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies.

At light load currents, the controller operates in PFM mode, and the output voltage ripple is dependent on the output-capacitor value and the PFM peak inductor current. Higher output-capacitor values minimize the voltage ripple in PFM mode. To achieve the specified regulation performance and low output-voltage ripple, the DC-bias characteristic of ceramic capacitors must be considered. The effective capacitance of ceramic capacitors drops with increasing DC bias voltage.

TI recommends using small ceramic capacitors placed between the inductor and load with many vias to the power ground (PGND) plane for the output capacitors of the buck controllers. This solution typically provides the smallest and lowest cost solution available for D-CAP2 controllers.

The selection of the output capacitor is typically driven by the output transient response. Equation 4 provides a rough estimate of the minimum required capacitance to ensure proper transient response. Because the transient response is significantly affected by the board layout, some experimentation is expected to confirm that values derived in this section are applicable to any particular use case. Equation 4 is not meant to be an absolute requirement, but rather a rough starting point. Alternatively, some known combination values from which to begin are provided in Table 6-1.

Equation 4.

where

• I_TRAN(MAX) is the maximum load current step.
• L is the chosen inductance.
• V_OUT is the minimum programmed output voltage.
• V_IN is the maximum input voltage.
• V_UNDER is the minimum allowable undershoot from the programmable voltage.

In cases where the transient current change is very low, the DC stability may become important. Use Equation 5 to calculate the approximate amount of capacitance required to maintain DC stability. Again, this equation is provided as a starting point; actual values will vary on a board-to-board case.

Equation 5.

where

• V_OUT is the maximum programmed output voltage
• 50 µs is based on internal ramp setup
• V_IN is the minimum input voltage
• f_SW is the typical switching frequency
• L is the chosen inductance

The maximum valuable between Equation 4 and Equation 5 must be selected. Table 6-1 lists some known inductor-capacitor combinations.

6.2.2.1.4 Selecting the FETs

This controller is designed to drive two NMOS FETs. Typically, lower R_DSON values are better for improving the overall efficiency of the controller; however, higher gate-charge thresholds result in lower efficiency so the twovalues must be balanced for optimal performance. As the R_DSON for the low-side FET decreases, the minimum current limit increases; therefore, appropriately select the values for the FETs, inductor, output capacitors, and current limit resistor. TI's CSD87331Q3D, CSD87381P, and CSD87588N devices are recommended for the controllers, depending on the required maximum current.

6.2.2.1.5 Bootstrap Capacitor

To ensure the internal high-side gate drivers are supplied with a stable low-noise supply voltage, a capacitor must be connected between the SWx pins and the respective BOOTx pins. TI recommends placing ceramic capacitors with a value of 0.1 µF for the controllers. During testing, a 0.1-µF, size 0402, 10-V capacitor is used for the controllers.

TI recommends reserving a small resistor in series with the bootstrap capacitor in case the turnon and turnoff of the FETs must be slowed to reduce voltage ringing on the switch node, which is a common practice for controller design.

6.2.2.1.6 Setting the Current Limit

The current-limiting resistor value must be chosen based on Equation 1.

6.2.2.1.7 Selecting the Input Capacitors

Because of the nature of the switching controller with a pulsating input current, a low-ESR input capacitor is required for best input-voltage filtering and also for minimizing the interference with other circuits caused by high input-voltage spikes. For the controller, a typical 2.2-µF capacitor can be used for the DRV5V_x_x pin to support the transients on the driver. For the FET input, 10 µF of input capacitance (after derating) is recommended for most applications. To achieve the low-ESR requirement, a ceramic capacitor is recommended. However, the voltage rating and DC-bias characteristic of ceramic capacitors must be considered. For better input-voltage filtering, the input capacitor can be increased without any limit.

TI recommends placing a ceramic capacitor as close as possible to the FET across the respective VSYS and PGND pins of the FETs. The preferred capacitors for the controllers are two Murata GRM21BR61E226ME44: 22-µF, 0805, 25-V, ±20%, or similar capacitors.

6.2.2.2.1 Selecting the Inductor

Placement of an inductor between the external FETs and the output capacitors is required. Together, the inductor and output capacitors form a double pole in the control loop that contributes to stability. Additionally, the inductor is directly responsible for the output ripple, efficiency, and transient performance. As the inductance used increases, the ripple current decreases, which typically results in an increase in efficiency. However, with an increase in inductance used, the transient performance decreases. Finally, the inductor selected must be rated for appropriate saturation current, core losses, and DCR.

Equation 6.

With the chosen inductance value and the peak current for the inductor in steady state operation, I_L(MAX) can be calculated using Equation 7. The rated saturation current of the inductor must be higher than the I_L(MAX) current.

Equation 7.

6.2.2.2.2 Selecting the Output Capacitors

Ceramic capacitors with low ESR values are recommended because they provide the lowest output voltage ripple. The output capacitor requires either an X7R or X5R rating. Y5V and Z5U capacitors, aside from the wide variation in capacitance over temperature, become resistive at high frequencies.

At light load currents, the converter operates in PFM mode and the output voltage ripple is dependent on the output-capacitor value and the PFM peak inductor current. Higher output-capacitor values minimize the voltage ripple in PFM mode. To achieve the specified regulation performance and low output-voltage ripple, the DC-bias characteristic of ceramic capacitors must be considered. The effective capacitance of ceramic capacitors drops with increasing DC-bias voltage.

For the output capacitors of the buck converters, TI recommends placing small ceramic capacitors between the inductor and load with many vias to the PGND plane. This solution typically provides the smallest and lowest-cost solution available for D-CAP2 controllers.

The output capacitance must equal or exceed the minimum capacitance listed for BUCK3, BUCK4, and BUCK5 (assuming quality layout techniques are followed).

6.2.2.2.3 Selecting the Input Capacitors

Because of the nature of the switching converter with a pulsating input current, a low-ESR input capacitor is required for the best input-voltage filtering and for minimizing the interference with other circuits caused by high input-voltage spikes. For the PVINx pin, 2.5 µF of input capacitance (after derating) is required for most applications. A ceramic capacitor is recommended to achieve the low-ESR requirement. However, the voltage rating and DC-bias characteristic of ceramic capacitors must be considered. The input capacitor can be increased without any limit for better input-voltage filtering.

The preferred capacitor for the converters is one Samsung CL05A106MP5NUNC: 10-µF, 0402, 10-V, ±20%, or similar capacitor.