JAJSGV4D July   2015  – February 2019 TPS65917-Q1

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 チャネル 1 の機能図
  2. 2改訂履歴
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Attributes
      1.      Pin Attributes
    2. 3.2 Signal Descriptions
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics — LDO Regulators
    6. 4.6  Electrical Characteristics — SMPS1&2 in Dual-Phase Configuration
    7. 4.7  Electrical Characteristics — SMPS1, SMPS2, SMPS3, SMPS4, and SMPS5 Stand-Alone Regulators
    8. 4.8  Electrical Characteristics — Reference Generator (Bandgap)
    9. 4.9  Electrical Characteristics — 32-kHz RC Oscillators and SYNCCLKOUT Output Buffers
    10. 4.10 Electrical Characteristics — 12-Bit Sigma-Delta ADC
    11. 4.11 Electrical Characteristics — Thermal Monitoring and Shutdown
    12. 4.12 Electrical Characteristics — System Control Thresholds
    13. 4.13 Electrical Characteristics — Current Consumption
    14. 4.14 Electrical Characteristics — Digital Input Signal Parameters
    15. 4.15 Electrical Characteristics — Digital Output Signal Parameters
    16. 4.16 I/O Pullup and Pulldown Characteristics
    17. 4.17 Electrical Characteristics — I2C Interface
    18. 4.18 Timing Requirements — I2C Interface
    19. 4.19 Timing Requirements — SPI
    20. 4.20 Switching Characteristics — LDO Regulators
    21. 4.21 Switching Characteristics — SMPS1&2 in Dual-Phase Configuration
    22. 4.22 Switching Characteristics — SMPS1, SMPS2, SMPS3, SMPS4, and SMPS5 Stand-Alone Regulators
    23. 4.23 Switching Characteristics — Reference Generator (Bandgap)
    24. 4.24 Switching Characteristics — PLL for SMPS Clock Generation
    25. 4.25 Switching Characteristics — 32-kHz RC Oscillators and SYNCCLKOUT Output Buffers
    26. 4.26 Switching Characteristics — 12-Bit Sigma-Delta ADC
    27. 4.27 Typical Characteristics
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  Functional Block Diagram
    3. 5.3  Device State Machine
      1. 5.3.1  Embedded Power Controller
      2. 5.3.2  State Transition Requests
        1. 5.3.2.1 ON Requests
        2. 5.3.2.2 OFF Requests
        3. 5.3.2.3 SLEEP and WAKE Requests
      3. 5.3.3  Power Sequences
      4. 5.3.4  Device Power Up Timing
      5. 5.3.5  Power-On Acknowledge
        1. 5.3.5.1 POWERHOLD Mode
        2. 5.3.5.2 AUTODEVON Mode
      6. 5.3.6  BOOT Configuration
        1. 5.3.6.1 Boot Pin Usage and Connection
      7. 5.3.7  Reset Levels
      8. 5.3.8  INT
      9. 5.3.9  Warm Reset
      10. 5.3.10 RESET_IN
    4. 5.4  Power Resources (Step-Down and Step-Up SMPS Regulators, LDOs)
      1. 5.4.1 Step-Down Regulators
        1. 5.4.1.1 Output Voltage and Mode Selection
        2. 5.4.1.2 Clock Generation for SMPS
        3. 5.4.1.3 Current Monitoring and Short Circuit Detection
        4. 5.4.1.4 POWERGOOD
        5. 5.4.1.5 DVS-Capable Regulators
          1. 5.4.1.5.1 Non DVS-Capable Regulators
        6. 5.4.1.6 Step-Down Converters SMPS1, SMPS2 or SMPS1&2
        7. 5.4.1.7 Step-Down Converters SMPS3, SMPS4, and SMPS5
      2. 5.4.2 Low Dropout Regulators (LDOs)
        1. 5.4.2.1 LDOVANA
        2. 5.4.2.2 LDOVRTC
        3. 5.4.2.3 LDO1 and LDO2
        4. 5.4.2.4 Low-Noise LDO (LDO5)
        5. 5.4.2.5 Other LDOs
    5. 5.5  SMPS and LDO Input Supply Connections
    6. 5.6  First Supply Detection
    7. 5.7  Long-Press Key Detection
    8. 5.8  12-Bit Sigma-Delta General-Purpose ADC (GPADC)
      1. 5.8.1 Asynchronous Conversion Request (SW)
      2. 5.8.2 Periodic Conversion (AUTO)
      3. 5.8.3 Calibration
    9. 5.9  General-Purpose I/Os (GPIO Pins)
    10. 5.10 Thermal Monitoring
      1. 5.10.1 Hot-Die Function (HD)
      2. 5.10.2 Thermal Shutdown
    11. 5.11 Interrupts
    12. 5.12 Control Interfaces
      1. 5.12.1 I2C Interfaces
        1. 5.12.1.1 I2C Implementation
        2. 5.12.1.2 F/S Mode Protocol
        3. 5.12.1.3 HS Mode Protocol
      2. 5.12.2 Serial Peripheral Interface (SPI)
        1. 5.12.2.1 SPI Modes
        2. 5.12.2.2 SPI Protocol
    13. 5.13 OTP Configuration Memory
    14. 5.14 Watchdog Timer (WDT)
    15. 5.15 System Voltage Monitoring
    16. 5.16 Register Map
      1. 5.16.1 Functional Register Mapping
    17. 5.17 Device Identification
  6. 6Applications, Implementation, and Layout
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 SMPS Input Capacitors
        2. 6.2.2.2 SMPS Output Capacitors
        3. 6.2.2.3 SMPS Inductors
        4. 6.2.2.4 LDO Input Capacitors
        5. 6.2.2.5 LDO Output Capacitors
        6. 6.2.2.6 VCCA
          1. 6.2.2.6.1 Meeting the Power-Down Sequence
          2. 6.2.2.6.2 Maintaining Sufficient Input Voltage
        7. 6.2.2.7 VIO_IN
        8. 6.2.2.8 GPADC
      3. 6.2.3 Application Curves
    3. 6.3 Layout
      1. 6.3.1 Layout Guidelines
      2. 6.3.2 Layout Example
    4. 6.4 Power Supply Coupling and Bulk Capacitors
  7. 7デバイスおよびドキュメントのサポート
    1. 7.1 デバイス・サポート
      1. 7.1.1 Third-Party Products Disclaimer
      2. 7.1.2 デバイスの項目表記
    2. 7.2 ドキュメントのサポート
      1. 7.2.1 関連資料
    3. 7.3 ドキュメントの更新通知を受け取る方法
    4. 7.4 Community Resources
    5. 7.5 商標
    6. 7.6 静電気放電に関する注意事項
    7. 7.7 Glossary
  8. 8メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGZ|48
サーマルパッド・メカニカル・データ
発注情報

2 改訂履歴

Changes from C Revision (March 2017) to D Revision

  • Added footnote recommending not to pull open-drain GPIOs up to an always-on voltage domainGo
  • Clarified that LDO1 and LDO2 input pins are not included in this minimum recommended operating voltage. See Electrical Characteristics: LDO Regulators for more information. Go
  • Added LDO and SMPS output capacitance footnoteGo
  • Added SMPS Output voltage slew rate description Go
  • Changed the comparison condition from VCCA to VCC_SENSE in the Embedded Power Controller sectionGo
  • Added typical debounce time from POWERHOLD to the enable of the first rail in the power sequence. Go
  • Changed discharge resistance to match electrical characteristics tableGo
  • Changed description of clock dithering from internal to external onlyGo
  • Added information about shutdown timing during short circuit detectionGo
  • Updated POWERGOOD block diagram and description to clarify dual phase operation. Go
  • Added notes to the SMPS Controls for DVS imageGo
  • Added the equation to convert GPADC code to internal die temperature in the 12-Bit Sigma-Delta General-Purpose ADC (GPADC) sectionGo
  • Additional description of VSYS_LO functionality Go
  • Added details on identifying device version. Go
  • SMPS and LDO output capacitance specification further explained Go
  • Added design considerations for VCCA capacitance to support loss of powerGo
  • Corrected 9-Vpp with 7V absolute maximum specification in the Layout Guidelines sectionGo
  • Updated requirements relating to measurement of high-side and low-side FETs in the Layout Guidelines sectionGo
  • Updated images and description on differential measurements across high-side and low-side FETs Go

Changes from B Revision (November 2015) to C Revision

  • 完全なデータシートの最初の公開リリースGo
  • Added recommendation for external pulldown resistor on the LDOVRTC_OUT pin in the Pin Attributes tableGo
  • Added OTP to the PU/PD selection for GPIO_1 as NRESWARM in the Signal Descriptions table Go
  • Changed the caption of the SMPS Efficiency For SMPS1 and SMPS 2 in Dual-Phase PWM Mode graph to SMPS Load Regulation for SMPS1 and SMPS2 Single-Phase PWM Mode in the Typical Characteristics sectionGo
  • Added the SMPS Load regulation for SMPS3, PWM Mode graph to the Typical Characteristics sectionGo
  • Changed single-phase to dual-phase and increased the output current to 7 A in the SMPS Load Regulation for SMPS12 graph in the Typical Characteristics sectionGo
  • Changed the debounce for PWRON to N/A in the ON Requests tableGo
  • Added description of VIO power-up timing in the Device Power Up Timing sectionGo
  • Changed the description of the LDOVRTC when in the BACKUP and OFF states and added a note in the LDOVRTC section Go
  • Added the note and pulldown equations to the System Voltage Monitoring sectionGo
  • Changed the SMPS1 voltage, SMPS2 voltage, and LDO2 voltage in the Design Parameters table Go
  • Changed 「静電放電に関する警告」声明Go

Changes from A Revision (November 2015) to B Revision

  • Added statement to the Current Monitoring and Short Circuit Detection section that the SMPS_SHORT_REGISTER bit will keep a resource off until it is cleared Go

Changes from * Revision (July 2015) to A Revision

  • Deleted the PPU type and changed the connection from floating to VRTC for the GPIO_1 pin when used only as an input with the secondary function as NRESWARM Go
  • Updated Max value of Device Off Mode Current Consumption from 45 µA to 55 µA Go
  • Changed the units for the x axis from mA to A in graphs D002 to D008 in the Typical Characteristics sectionGo
  • Added register names for the GPADC channel 3 D1 & D2 trim when HIGH_VCC_SENSE = 1Go