JAJSPC8C December   2022  – February 2024 TPSM33615 , TPSM33625

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 絶対最大定格
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 電気的特性
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range
      2. 7.3.2  Output Voltage Selection
      3. 7.3.3  Input Capacitors
      4. 7.3.4  Output Capacitors
      5. 7.3.5  Enable, Start-Up, and Shutdown
      6. 7.3.6  External CLK SYNC (with MODE/SYNC)
        1. 7.3.6.1 Pulse-Dependent MODE/SYNC Pin Control
      7. 7.3.7  Switching Frequency (RT)
      8. 7.3.8  Power-Good Output Operation
      9. 7.3.9  Internal LDO, VCC and VOUT/FB Input
      10. 7.3.10 Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)
      11. 7.3.11 Spread Spectrum
      12. 7.3.12 Soft Start and Recovery from Dropout
        1. 7.3.12.1 Recovery from Dropout
      13. 7.3.13 Overcurrent Protection (Hiccup Mode)
      14. 7.3.14 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 CCM Mode
        2. 7.4.3.2 Auto Mode – Light-Load Operation
          1. 7.4.3.2.1 Diode Emulation
          2. 7.4.3.2.2 Frequency Reduction
        3. 7.4.3.3 FPWM Mode – Light-Load Operation
        4. 7.4.3.4 Minimum On-Time (High Input Voltage) Operation
        5. 7.4.3.5 Dropout
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Choosing the Switching Frequency
        3. 8.2.2.3  Setting the Output Voltage
        4. 8.2.2.4  Input Capacitor Selection
        5. 8.2.2.5  Output Capacitor Selection
        6. 8.2.2.6  VCC
        7. 8.2.2.7  CFF Selection
        8. 8.2.2.8  Power Good Signal
        9. 8.2.2.9  Maximum Ambient Temperature
        10. 8.2.2.10 Other Connections
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Ground and Thermal Considerations
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
      3. 9.1.3 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.6 External CLK SYNC (with MODE/SYNC)

Synchronizing the operation of multiple regulators in a single system, resulting in a well-defined system level performance is desirable. The select variants in the TPSM336x5 with the MODE/SYNC pin allow the power designer to synchronize the device to a common external clock. An in-phase locking scheme where the rising edge of the clock signal, provided to the MODE/SYNC pin, corresponds to the turning on of the high-side device. The external clock synchronization is implemented using a phase locked loop (PLL) eliminating any large glitches. The external clock fed into the TPSM336x5 replaces the internal free-running clock, but does not affect any frequency foldback operation. Output voltage continues to be well-regulated. The device remains in FPWM mode and operates in CCM for light loads when synchronization input is provided.

The MODE/SYNC input pin in the TPSM336x5 can operate in one of three selectable modes:

  • Auto Mode: Pulse frequency modulation (PFM) operation is enabled during light load and diode emulation prevents reverse current through the inductor.
  • FPWM Mode: In FPWM mode, diode emulation is disabled, allowing current to flow backwards through the inductor. This allows operation at full frequency even without load current.
  • SYNC Mode: The internal clock locks to an external signal applied to the MODE/SYNC pin. As long as output voltage can be regulated at full frequency and is not limited by minimum off-time or minimum on-time, clock frequency is matched to the frequency of the signal applied to the MODE/SYNC pin. While the device is in SYNC mode, it operates as though in FPWM mode: diode emulation is disabled allowing the frequency applied to the MODE/SYNC pin to be matched without a load.