JAJSPL6A October   2023  – December 2023 TPSM365R1 , TPSM365R15

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable, Shutdown, and Start-Up
      2. 7.3.2  External CLK SYNC (With MODE/SYNC)
        1. 7.3.2.1 Pulse Dependent MODE/SYNC Pin Control
      3. 7.3.3  Adjustable Switching Frequency (with RT)
      4. 7.3.4  Power-Good Output Operation
      5. 7.3.5  Internal LDO, VCC UVLO, and VOUT/FB Input
      6. 7.3.6  Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)
      7. 7.3.7  Output Voltage Selection
      8. 7.3.8  Spread Spectrum
      9. 7.3.9  Soft Start and Recovery from Dropout
        1. 7.3.9.1 Soft Start
        2. 7.3.9.2 Recovery from Dropout
      10. 7.3.10 Current Limit and Short Circuit
      11. 7.3.11 Thermal Shutdown
      12. 7.3.12 Input Supply Current
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 CCM Mode
        2. 7.4.3.2 AUTO Mode - Light Load Operation
          1. 7.4.3.2.1 Diode Emulation
          2. 7.4.3.2.2 Frequency Reduction
        3. 7.4.3.3 FPWM Mode - Light Load Operation
        4. 7.4.3.4 Minimum On-time Operation
        5. 7.4.3.5 Dropout
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Choosing the Switching Frequency
        3. 8.2.2.3  Setting the Output Voltage
        4. 8.2.2.4  Input Capacitor Selection
        5. 8.2.2.5  Output Capacitor Selection
        6. 8.2.2.6  VCC
        7. 8.2.2.7  CFF Selection
        8. 8.2.2.8  External UVLO
        9. 8.2.2.9  Power-Good Signal
        10. 8.2.2.10 Maximum Ambient Temperature
        11. 8.2.2.11 Other Connections
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.7 Output Voltage Selection

In the TPSM365R1x, each variant can be configured as a fixed output voltage or an adjustable output voltage. During device initialization the device configures the target output voltage to an internally selected value or an adjustable version by detecting if feedback resistors are present. When configuring the output voltage to be fixed value, simply connect the VOUT/FB pin to the system output voltage node. See Section 4 for the fixed output voltage setting of each variant.

To configure an adjustable output voltage, external feedback resistors are required as shown in Figure 7-8. By connecting external feedback resistors with a parallel resistance greater than 5 kΩ but less than or equal to
10 kΩ (see Equation 2) the output voltage is set according as needed. The internal voltage reference is 1 V. Refer to Section 8.2.2.3 for more details on how to adjust the output voltage.

GUID-4DA1D67E-C6E5-4E5E-AE8A-CB21526B3374-low.gifFigure 7-8 Setting Output Voltage for Adjustable Output Variant
Equation 2. 5 kΩ < RFBT||RFBB ≤10 kΩ

  • RFBT is the top resistor of the feedback divider
  • RFBB is the bottom resistor of the feedback divider

When configured in adjustable output voltage mode, an addition feed-forward capacitor, CFF, in parallel with the RFBT, can be used to optimize the phase margin and transient response. See Section 8.2.2.7 for more details. No additional resistor divider or feed-forward capacitor, CFF, is needed in fixed-output variants.

Please refer to Table 7-4 for selecting passive component values for typical, output voltages.

Table 7-4 Standard RFBT Values, Recommended FSW and Minimum COUT
VOUT (V) RFBT (kΩ) RFBB (kΩ) RECOMMENDED FSW (kHz) COUT(MIN) (µF) (EFFECTIVE) VOUT (V) RFBT (kΩ) RFBB (kΩ) RECOMMENDED FSW (kHz) COUT(MIN) (µF) (EFFECTIVE)
1.0 10 DNP 300 47 3.3 33.2 14.3 1000 4.7
1.2 12.1 60.4 300 47 5.0 49.9 12.4 1000 4.7
1.5 15 30.1 400 33 7.5 75 11.5 1500 2.2
1.8 18.2 22.6 500 33 10 100 11 1800 2.2
2.0 20 20 500 22 12 121 10.7 2200 2.2
2.5 24.9 16.5 500 22 13 130 10.7 2200 2.2
3.0 30 15 800 4.7 15 150 10.7 2200 2.2