JAJSSK4A December   2023  – June 2024 TPSM64404 , TPSM64406 , TPSM64406E

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN1, VIN2)
      2. 7.3.2  Enable EN Pin and Use as VIN UVLO
      3. 7.3.3  CONFIG Device Configuration Pin
      4. 7.3.4  Adjustable Switching Frequency
      5. 7.3.5  Spread Spectrum
      6. 7.3.6  Adjustable Output Voltage (FB)
      7. 7.3.7  Input Capacitors
      8. 7.3.8  Output Capacitors
      9. 7.3.9  SYNC Allows Clock Synchronization and Mode Selection
      10. 7.3.10 Power-Good Output Voltage Monitoring
      11. 7.3.11 Bias Supply Regulator (VCC, VOSNS)
      12. 7.3.12 Overcurrent Protection (OCP)
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1 – High-efficiency Dual Output 5 V at 3 A, 3.3 V at 3 A, Synchronous Buck Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2 Output Voltage Setpoint
          3. 8.2.1.2.3 Switching Frequency Selection
          4. 8.2.1.2.4 Input Capacitor Selection
          5. 8.2.1.2.5 Output Capacitor Selection
          6. 8.2.1.2.6 Other Considerations
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 1 – High-efficiency 8-A (10-A peak) Synchronous Buck Regulator for Industrial Applications
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Output Voltage Setpoint
          2. 8.2.2.2.2 Switching Frequency Selection
          3. 8.2.2.2.3 Input Capacitor Selection
          4. 8.2.2.2.4 Output Capacitor Selection
          5. 8.2.2.2.5 Other Connections
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Design and Layout
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.10 Power-Good Output Voltage Monitoring

While the PG1/PG2 of the TPSM6440X resembles a standard power-good function, the functionality is designed to replace a discrete reset IC, reducing BOM cost. There are three major differences between the PG function and the normal power-good function seen in most regulators:

  • A delay has been added for release of reset. See Table 7-7.
  • PG output signals a fault (pulls the output to ground) while the part is disabled.
  • PG continues to operate with input voltage as low as 1.2 V. Below this input voltage, PG output can be high impedance.

For dual output configuration (RCONFIG = 0 or 121 kΩ), The PG1 is an open-drain and must be tied through a resistor to an external voltage, and pulls low if the monitors on FB1 or VOSNS1 trip. The PG2 flag is configured in the same manner as PG1 and monitors the second output at either FB2 or VOSNS2.

For single-output multiphase operation (9.53 kΩ < RCONFIG < 93.1 kΩ), PG2 is re-configured as SYNC-OUT to provide a phase shifted clock to the secondary devices. In this configuration, the PG2/SYNC-OUT terminal of the primary device can be left floating for dual phase operation or tied to the SYNC pin of the secondary device for more than four-phases. For six-phase operation the PG2/SYNC-OUT pin of the secondary device is connected to the SYNC pin of the tertiary device.

TPSM64404 TPSM64406 TPSM64406E PG Static Voltage Thresholds Figure 7-9 PG Static Voltage Thresholds
TPSM64404 TPSM64406 TPSM64406E PG Timing Diagram (Excludes OV Events) Figure 7-10 PG Timing Diagram (Excludes OV Events)
Table 7-7 Conditions that Cause PG to Signal a Fault (Pull Low)
FAULT CONDITION INITIATED FAULT CONDITION ENDS (AFTER WHICH tRESET_ACT MUST PASS BEFORE RESET OUTPUT IS RELEASED)
FB below VRESET_UV for longer than tRESET_FILTER FB above VRESET_UV + VRESET_HYST for longer than tRESET_FILTER
FB above VRESET_OV for longer than tRESET_FILTER FB below VRESET_OV – VRESET_HYST for longer than tRESET_FILTER
Junction temperature exceeds TSD_R Junction temperature falls below TSD_F(1)
EN low tEN passes after EN becomes high(1)
VIN falls low enough so that VCC falls below VCC_UVLO - VCC_UVLO_HYST. This value is called VIN_OPERATE. Voltage on VIN is high enough so that VCC pin exceed VCC_UVLO(1)
(1) As an additional operational check, PG remains low during soft start. Soft start is defined as until the lesser of either full output voltage reached or tSS2 has passed since initiation. This definition is true even if all other conditions in this table are met and tRESET_ACT has passed. Lockout during soft start does not require tRESET_ACT to pass before PG is released.

The threshold voltage for the PG function is specified to take advantage of the availability of the internal feedback threshold to the PG circuit. This allows a maximum threshold of 96.5% of selected output voltage to be specified at the same time as 96% of actual operating point. The net result is a more accurate reset function while expanding the system allowance for transient response. See the output voltage error stack-up comparison in Figure 7-11.

In addition to signaling a fault upon overvoltage detection (FB above VRESET_OV), the switch node is shut down and a small, approximately 1-mA pulldown is applied to the SW node.

TPSM64404 TPSM64406 TPSM64406E Reset Threshold Voltage Stack-up Figure 7-11 Reset Threshold Voltage Stack-up

The PG signal can be used for start-up sequencing of downstream regulators, as shown in the following figure, or for fault protection and output monitoring.

TPSM64404 TPSM64406 TPSM64406E TPSM64406 Sequencing Implementation Using PG and EN| Figure 7-12 TPSM64406 Sequencing Implementation Using PG and EN|