JAJSSK4A December 2023 – June 2024 TPSM64404 , TPSM64406 , TPSM64406E
PRODUCTION DATA
Table 8-3 shows the intended input, output, and performance parameters for this application example.
DESIGN PARAMETER | VALUE |
---|---|
Input voltage range | 6.3 V to 36 V |
Input voltage UVLO turn on/off | 6 V, 4.3 V |
Output voltage 1 | 5 V |
Output voltage 2 | 3.3 V |
Full-load current 1 | 3 A |
Full-load current 2 | 3 A |
Switching frequency | 1 MHz |
Output voltage regulation | ±1% |
Table 8-4 provides the selected buck module power-stage components with availability from multiple vendors. This design uses an all-ceramic output capacitor implementation.
REF DES | QTY | SPECIFICATION | MANUFACTURER(1) | PART NUMBER |
---|---|---|---|---|
CIN1, CIN2 | 4 | 10 µF, 50 V, X5R, 0805, ceramic | Murata | GRM21BR61H106ME43L |
CINBULK | 1 | 100 µF, 50 V electrolytic | Panasonic | EEE-FK1H101P |
COUT1, COUT2 | 4 | 22 µF, 25 V, X7R, 1210, ceramic | Murata | GRM32ER71E226KE15L |
2 | 1 µF, 25 V, X7R, 0603, ceramic | Murata | GCM188R71E105KA64D | |
U1 | 1 | TPSM64406 36-V, 6-A synchronous buck module | Texas Instruments | TPSM64406RDLR |