JAJSSK4A December   2023  – June 2024 TPSM64404 , TPSM64406 , TPSM64406E

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN1, VIN2)
      2. 7.3.2  Enable EN Pin and Use as VIN UVLO
      3. 7.3.3  CONFIG Device Configuration Pin
      4. 7.3.4  Adjustable Switching Frequency
      5. 7.3.5  Spread Spectrum
      6. 7.3.6  Adjustable Output Voltage (FB)
      7. 7.3.7  Input Capacitors
      8. 7.3.8  Output Capacitors
      9. 7.3.9  SYNC Allows Clock Synchronization and Mode Selection
      10. 7.3.10 Power-Good Output Voltage Monitoring
      11. 7.3.11 Bias Supply Regulator (VCC, VOSNS)
      12. 7.3.12 Overcurrent Protection (OCP)
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1 – High-efficiency Dual Output 5 V at 3 A, 3.3 V at 3 A, Synchronous Buck Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2 Output Voltage Setpoint
          3. 8.2.1.2.3 Switching Frequency Selection
          4. 8.2.1.2.4 Input Capacitor Selection
          5. 8.2.1.2.5 Output Capacitor Selection
          6. 8.2.1.2.6 Other Considerations
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 1 – High-efficiency 8-A (10-A peak) Synchronous Buck Regulator for Industrial Applications
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Output Voltage Setpoint
          2. 8.2.2.2.2 Switching Frequency Selection
          3. 8.2.2.2.3 Input Capacitor Selection
          4. 8.2.2.2.4 Output Capacitor Selection
          5. 8.2.2.2.5 Other Connections
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Design and Layout
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.6 Adjustable Output Voltage (FB)

The TPSM64406 has an adjustable output voltage range from 0.8 V up to a maximum of 16 V or slightly less than VIN, whichever is lower. Setting the output voltage requires two feedback resistors, designated as RFBT and RFBB in Figure 7-1. The reference voltage at the feedback (FB) pin is set at 0.8 V with a feedback system accuracy over the full junction temperature range of ±1%. The junction temperature range for the device is –40°C to 125°C.

Calculate the value for RFBB using Equation 4 below based on a recommended value for RFBT of 100 kΩ.

Equation 4. R F B B k Ω =   R F B T k Ω V O U T 0.8 - 1  

Table 7-4 lists the standard resistor values for several output voltages and the recommended switching frequency range to maintain reasonable peak-to-peak inductor ripple current. This table also includes the minimum required output capacitance for each output voltage setting to maintain stability. The capacitances as listed represent effective values for ceramic capacitors derated for DC bias voltage and temperature. Furthermore, place a feedforward capacitor, CFF, in parallel with RFBT to increase the phase margin when the output capacitance is close to the minimum recommended value.

Table 7-4 Standard RFBT Values, Recommended FSW Range and Minimum COUT
VOUT (V) RFBT (kΩ) (1) RFBB (kΩ) (1) SUGGESTED FSW RANGE (kHz) COUT(min) (µF), Per Phase (EFFECTIVE) BOM(2) CFF (pF)
0.8 10 Open 300 to 700 470 1 × 47 μF (6.3 V), 1 × 470 μF (2.5 V) —
1.8 12.4 10 300 to 1000 125 3 × 47 μF (6.3 V), 1 × 22 μF (6.3 V) 330
3.3 31.2 10 500 to 1300 64 4 × 22 μF (10 V) Internal
5 52.3 10 700 to 2100 64 4 × 22 μF (10 V) Internal
9 105 10 1200 to 2100 40 3 × 22 μF (16 V) 4.7
12 140 10 1700 to 2100 30 1 × 22 μF (25 V), 1 × 50 μF (25 V) 10
16 190 10 1900 to 2100 20 1 × 22 μF (25 V), 1 × 50 μF (25 V) —
(1) RFBT = 100 kΩ.
(2) Refer to Table 7-6 for the output capacitor list.

Note that higher feedback resistances consume less DC current. However, an upper RFBT resistor value higher than 1 MΩ renders the feedback path more susceptible to noise. Higher feedback resistances generally require more careful layout of the feedback path. Make sure to locate the feedback resistors close to the FB and AGND pins, keeping the feedback trace as short as possible (and away from noisy areas of the PCB). See Layout Example guidelines for more detail.