JAJSSK4A December   2023  – June 2024 TPSM64404 , TPSM64406 , TPSM64406E

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN1, VIN2)
      2. 7.3.2  Enable EN Pin and Use as VIN UVLO
      3. 7.3.3  CONFIG Device Configuration Pin
      4. 7.3.4  Adjustable Switching Frequency
      5. 7.3.5  Spread Spectrum
      6. 7.3.6  Adjustable Output Voltage (FB)
      7. 7.3.7  Input Capacitors
      8. 7.3.8  Output Capacitors
      9. 7.3.9  SYNC Allows Clock Synchronization and Mode Selection
      10. 7.3.10 Power-Good Output Voltage Monitoring
      11. 7.3.11 Bias Supply Regulator (VCC, VOSNS)
      12. 7.3.12 Overcurrent Protection (OCP)
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1 – High-efficiency Dual Output 5 V at 3 A, 3.3 V at 3 A, Synchronous Buck Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2 Output Voltage Setpoint
          3. 8.2.1.2.3 Switching Frequency Selection
          4. 8.2.1.2.4 Input Capacitor Selection
          5. 8.2.1.2.5 Output Capacitor Selection
          6. 8.2.1.2.6 Other Considerations
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 1 – High-efficiency 8-A (10-A peak) Synchronous Buck Regulator for Industrial Applications
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Output Voltage Setpoint
          2. 8.2.2.2.2 Switching Frequency Selection
          3. 8.2.2.2.3 Input Capacitor Selection
          4. 8.2.2.2.4 Output Capacitor Selection
          5. 8.2.2.2.5 Other Connections
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Design and Layout
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
8.2.2.2.3 Input Capacitor Selection

The TPSM64406 requires a minimum input capacitance of 4 × 10 µF ceramic, preferably with X7R dielectric. The voltage rating of input capacitors must be greater than the maximum input voltage. For this design, select four 10-µF, X7R, 50-V, 0805 case size, ceramic capacitors connected from VIN1 and VIN2 to PGND as close as possible to the module. See Figure 8-24 for recommended layout placement.