JAJSSK4A December 2023 – June 2024 TPSM64404 , TPSM64406 , TPSM64406E
PRODUCTION DATA
The following table shows the intended input, output, and performance parameters for this application example. Note that if the input voltage decreases below approximately 7 V, the regulator operates in dropout with the output voltage below the 5-V setpoint.
DESIGN PARAMETER | VALUE |
---|---|
Input voltage range | 7 V to 36 V |
Input voltage UVLO turn on/off | 6 V, 4.3 V |
Output voltage | 5 V |
Maximum output current | 6 A |
Switching frequency | 2.1 MHz |
Output voltage regulation | ±1% |
Module shutdown current | < 1 µA |
Table 8-4 provides the selected buck module power-stage components with availability from multiple vendors. This design uses an all-ceramic output capacitor implementation.
REFERENCE DESIGNATOR | QTY | SPECIFICATION | MANUFACTURER(1) | PART NUMBER |
---|---|---|---|---|
CIN1, CIN2 | 4 | 2.2 µF, 50 V, X7R, 0805, ceramic | TDK | C2012X7R1H225K125AC |
CINBULK | 1 | 100 µF, 50 V electrolytic | Panasonic | EEE-FK1H101P |
COUT1, COUT2 | 5 | 10 µF, 25 V, X7R, 1210, ceramic | TDK | C3225X7R1E106K250AC |
1 | 22 µF, 25 V, X7R, 1210, ceramic | TDK | CNA6P1X7R1E226M250AE | |
U1 | 1 | TPSM64406 36-V, 6-A synchronous buck module | Texas Instruments | TPSM64406RDLR |
More generally, the TPSM64406 module is designed to operate with a wide range of external components and system parameters. However, the integrated loop compensation is optimized for a certain range of output capacitance.