JAJSSK4A December   2023  – June 2024 TPSM64404 , TPSM64406 , TPSM64406E

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN1, VIN2)
      2. 7.3.2  Enable EN Pin and Use as VIN UVLO
      3. 7.3.3  CONFIG Device Configuration Pin
      4. 7.3.4  Adjustable Switching Frequency
      5. 7.3.5  Spread Spectrum
      6. 7.3.6  Adjustable Output Voltage (FB)
      7. 7.3.7  Input Capacitors
      8. 7.3.8  Output Capacitors
      9. 7.3.9  SYNC Allows Clock Synchronization and Mode Selection
      10. 7.3.10 Power-Good Output Voltage Monitoring
      11. 7.3.11 Bias Supply Regulator (VCC, VOSNS)
      12. 7.3.12 Overcurrent Protection (OCP)
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1 – High-efficiency Dual Output 5 V at 3 A, 3.3 V at 3 A, Synchronous Buck Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2 Output Voltage Setpoint
          3. 8.2.1.2.3 Switching Frequency Selection
          4. 8.2.1.2.4 Input Capacitor Selection
          5. 8.2.1.2.5 Output Capacitor Selection
          6. 8.2.1.2.6 Other Considerations
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 1 – High-efficiency 8-A (10-A peak) Synchronous Buck Regulator for Industrial Applications
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Output Voltage Setpoint
          2. 8.2.2.2.2 Switching Frequency Selection
          3. 8.2.2.2.3 Input Capacitor Selection
          4. 8.2.2.2.4 Output Capacitor Selection
          5. 8.2.2.2.5 Other Connections
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Design and Layout
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

TJ = –40°C to 125°C. Typical values are at TJ = 25°C and VIN = 13.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ(VIN-ST5p0) VIN quiescent current, single output mode Non-switching, VEN = 2 V, VBIAS = VVOSNS1 = 5 V + 10%, TJ = 125℃ 25 45 µA
IQ(VIN-ST3p3) VIN quiescent current, single output mode Non-switching, VEN = 2 V, VBIAS = VVOSNS1 = 3.3 V + 10%, TJ = 125℃ 15 35 µA
IQ(VIN-DT3p3) VIN quiescent current, dual output mode, BIAS = 3.3 V Non-switching, VEN = 2 V, VBIAS = VVOSNS1 = 3.3 V + 10%, VVOSNS2 = 5 V + 10%, TJ = 125℃ 9 18 µA
ISD(VIN) VIN shutdown supply current VEN = 0 V 1 8 µA
UVLO
VINUVLO(R) VIN UVLO rising threshold VIN rising 3.5 3.80 V
VINUVLO(F) VIN UVLO falling threshold VIN falling 2.55 3 V
VINUVLO(H) VIN UVLO hysteresis 0.735 0.95 1.25 V
ENABLE
VEN(R) EN1/2 voltage rising threshold EN1/2 rising, enable switching 1.125 1.25 1.375 V
VEN(F) EN1/2 voltage falling threshold EN1/2 falling, disable switching 0.8 0.9 1.0 V
VEN(H) EN1/2 voltage hysteresis 0.25 0.325 0.55 V
VEN(W) EN1/2 voltage wake-up threshold 0.4 V
IEN EN1/2 pin sourcing current post EN rising threshold VEN1/2 = VIN = 13.5 V 0.6 400 nA
INTERNAL LDO
VVCC Internal LDO output voltage VBIAS ≥ 3.4 V, IVCC ≤ 100 mA 2.7 3.1 3.7 V
IVCC Internal LDO short-circuit current limit VIN = 13.5 V 100 377 880 mA
VVCC(UVLO-R) VCC UVLO rising threshold for Start-up 3.3 3.5 3.75 V
VVCC(UVLO-F) VCC UVLO falling threshold for Shutdown 2.3 2.5 2.7 V
REFERENCE VOLTAGE
VFB1/2 Dual output feedback voltages in adjustable output configuration 788 800 812 mV
VFB1_so Single Output mode FB voltage in adjustable output configuration 788 800 812 mV
IFB1/2(LKG) FB input leakage current in dual output configuration VFB1/2 = 0.8 V 10 250 nA
IFB1_so(LKG) FB input leakage current in single output configuration VFB = 0.8 V 2 250 nA
FBSel-5v0 Voltage threshold for fixed 5.0 V setting VCC-0.5 V
FBSel-3v0 Resistor for fixed 3.3 V setting 300 Ω
FBSel-ext Minimum Thevenin Equivalent resistance of external FB divider option to select adjustable output voltage. 4 kΩ
ERROR AMPLIFIER
gm-S1 EA transconductance - single output mode VFB1 = VCOMP 625 888 1300 µS
ICOMP(src) EA source current - single output mode VCOMP = 1 V, VFB1 = 0.4 V 92.5 200 400 µA
ICOMP(sink) EA sink current - single output mode VCOMP = 1 V, VFB1 = 1.2 V 94.5 200 500 µA
SWITCHING FREQUENCY
fSW1(FCCM) Switching frequency, FCCM operation RRT = 7.15 kΩ to AGND 1.9 2.1 2.3 MHz
fSW2(FCCM) Switching frequency, FCCM operation RRT = 39.2 kΩ to AGND  360 400 450 kHz
fADJ(FCCM) Adjustable switching frequency range RRT resistor from 6.81 kΩ to 158 kΩ to AGND 0.1 2.2 MHz
fSS(int) Spread Spectrum switching frequency range RRT = 7.15 kΩ, RCONFIG= 73.2 k Ω 10%
SYNCHRONIZATION
VIH(sync) SYNCIN High-level threshold 1.35 1.6 V
VIL(sync) SYNCIN Low-level threshold 0.65 0.95 V
VOH(sync) Sync output high voltage minimum 10 mA load 1.6 2.6 V
VOL(sync) Sync output low voltage maximum 10 mA load 0.34 0.68 V
fSYNC-2p1 Frequency sync range around 2.1 MHz RRT = 7.15 kΩ to AGND 1.7 2.1 2.4 MHz
fSYNC-0p4 Frequency sync range around 400 kHz RRT = 39.2 kΩ to AGND 320 400 480 kHz
tSYNC(min) Minimum pulse width of external synchronization signal above VIH(sync) 100 ns
tSYNC(max) Minimum width of low external synchronization signal below VIL(sync) 100 ns
tSYNC-SW(delay) Delay from SYNC rising edge to SW rising edge - single output mode - secondary 90 130 ns
STARTUP
tSS(R) Internal fixed soft-start time - dual output mode From VVOSNS1/2= 0% (first SW pulse) to VVOSNS1/2 = 90% 2.7 4.5 7 ms
tSS_Lockout(R) Time from first SW1/2 pulse to enable FPWM mode if output not in regulation - dual output mode 7 13 32 ms
ISS(R) Soft-start charge current - single output mode VSS = 0 V 15 20 25 µA
RSS(F) Soft-start discharge resistance - single output mode 10 27 Ω
tEN EN1 (Single output mode) or EN1/EN2 (whichever first in dual output mode) HIGH to start of switching delay 687 900 µs
POWER STAGE
RDSON(HS) High-side MOSFET on-resistance VBOOT-SW = 3.3 V, IOUT = 1 A 37 75 mΩ
RDSON(LS) Low-side MOSFET on-resistance VVCC = 3.3 V, IOUT = 1 A 23.9 50 mΩ
tON(min) Minimum ON pulse width VIN = 20 V, IOUT = 2 A 40 62 ns
tON(max) Maximum ON pulse width (dual output, single output primary) RRT = 7.15 kΩ 5 8 12 µs
tON(max) Maximum ON pulse width (Single output secondary) RRT = 7.15 kΩ 16 25 µs
tOFF(min) Minimum OFF pulse width VIN = 4 V 70 110 ns
OVERCURRENT PROTECTION
IHS(OC1) High-side peak current limit TPSM64404 Peak current limit on HS FET when Duty Cycle approaches 0%  4.76 A
IHS(OC2) High-side peak current limit TPSM64406 Peak current limit on HS FET when Duty Cycle approaches 0%  4.6 5.5 6.8 A
ILS(OC1) Low-side valley current limit TPSM64404 Valley current limit on LS FET 3.2 A
ILS(OC2) Low-side valley current limit TPSM64406 Valley current limit on LS FET 2.8 3.7 4.5 A
ILS2(NOC) Low-side negative current limit TPSM64406 Sinking current limit on LS FET 2 2.8 3.6 A
ILPEAK1(min-0) Minimum peak inductor current at minimum duty cycle TPSM64404 VVCC = 3.3 V, tpulse ≤ 100 ns 0.71 A
ILPEAK1(min-100) Minimum peak inductor current at maximum duty cycle TPSM64404 VVCC = 3.3 V, tpulse ≥ 1 µs 0.19 A
ILPEAK2(min-0) Minimum peak inductor current at minimum duty cycle TPSM64406 VVCC = 3.3 V, tpulse ≤ 100 ns 0.5 0.79 1.1 A
ILPEAK2(min-100) Minimum peak inductor current at maximum duty cycle TPSM64406 VVCC = 3.3 V, tpulse ≥ 1 µs 0.25 0.3 0.35 A
VHiccup-FB Hiccup threshold on FB pin - dual output mode, adjustable output option HS FET On-time > 165 ns 0.25 0.3 0.35 V
tHiccup-1 Wait time before entering Hiccup - single and dual output mode 126 128 130 Curent Limit cycles
tHiccup-2 Hiccup time before re-start 50 88 ms
POWER GOOD
VPGTH-1 Power Good threshold (PG1/2) PGOOD low, VVOSNS1/2 rising 93% 95% 97%
VPGTH-2 Power Good threshold (PG1/2) PGOOD high, VVOSNS1/2 falling  92% 94% 96%
VPGTH-3 Power Good threshold (PG1/2) PGOOD high, VVOSNS1/2 rising 105% 107% 110%
VPGTH-4 Power Good threshold (PG1/2) PGOOD low, VVOSNS1/2 falling 104% 106% 109%
tPGOOD(R) PG1/2 delay from VVOSNS1/2 valid to PGOOD high during start-up VVOSNS1/2 = 3.3 V 1.5 2.1 3 ms
tPGOOD(F) PG1/2 delay from VVOSNS1/2 invalid to PGOOD low  VVOSNS1/2 = 3.3 V 25 40 70 µs
IPG(LKG) PG1/2 pin leakage current when open drain output is high VPG = 3.3 V 0.075 µA
VPG-D(LOW) PG pin output low-level voltage for both channels  IPG = 1 mA, VEN = 0 V. 400 mV
RPG-1 Pull down MOSFET resistance IPG = 1 mA, VEN = 3.3 V. 30 90 Ω
VIN(PG_VALID) Minimum VIN for valid PG output Pull up resistance on PG - RPG = 10 kΩ, Voltage Pull up on PG - VPULLUP_PG= 3 V, VPG-D(LOW)= 0.4 V 0.45 1.2 V
THERMAL SHUTDOWN
TJ(SD) Thermal shutdown threshold (1) Temperature rising 160 170 180 °C
TJ(HYS) Thermal shutdown hysteresis (1) 10 °C
(1) Specified by design.