JAJSP69 November   2023 TPSM828510 , TPSM828511 , TPSM828512

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Schematic
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Precise Enable (EN)
      2. 8.3.2 MODE/SYNC
      3. 8.3.3 Undervoltage Lockout (UVLO)
      4. 8.3.4 Power-Good Output (PG)
      5. 8.3.5 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pulse Width Modulation (PWM) Operation
      2. 8.4.2 Power Save Mode Operation (PFM/PWM)
      3. 8.4.3 100% Duty-Cycle Operation
      4. 8.4.4 Current Limit and Short-Circuit Protection
      5. 8.4.5 Output Discharge
      6. 8.4.6 Soft Start / Tracking (SS/TR)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Programming the Output Voltage
        2. 9.2.2.2 Feedforward Capacitor
        3. 9.2.2.3 Input Capacitor
        4. 9.2.2.4 Output Capacitor
        5. 9.2.2.5 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Voltage Tracking
      2. 9.3.2 Synchronizing to an External Clock
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
        1. 9.5.2.1 Thermal Consideration
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.4 Power-Good Output (PG)

Power good is an open-drain output that requires a pullup resistor to any voltage up to the recommended input voltage level. Power good is driven by a window comparator. PG is held low when the device is

  • disabled,
  • in undervoltage lockout,
  • in thermal shutdown,
  • or in soft start.

When the output voltage is in regulation hence, within the window defined in the electrical characteristics, the PG output is high impedance. VIN must remain present for the PG pin to stay low. If the power-good output is not used, TI recommends to tie to GND or leave open. The PG indicator features a de-glitch, as specified in the electrical characteristics, for the transition from "high impedance" to "low" of the output.

Table 8-1 Power-Good Pin Logic
EN DEVICE STATUS PG LOGIC STATUS
X VIN < 2 V Undefined
Low VIN ≥ 2 V Low
High 2 V ≤ VIN < VUVLO OR in thermal shutdown OR VOUT not in regulation OR device in soft start Low
High VOUT in regulation High impedance