JAJSP69
November 2023
TPSM828510
,
TPSM828511
,
TPSM828512
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Device Comparison Table
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Typical Characteristics
7
Parameter Measurement Information
7.1
Schematic
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Precise Enable (EN)
8.3.2
MODE/SYNC
8.3.3
Undervoltage Lockout (UVLO)
8.3.4
Power-Good Output (PG)
8.3.5
Thermal Shutdown
8.4
Device Functional Modes
8.4.1
Pulse Width Modulation (PWM) Operation
8.4.2
Power Save Mode Operation (PFM/PWM)
8.4.3
100% Duty-Cycle Operation
8.4.4
Current Limit and Short-Circuit Protection
8.4.5
Output Discharge
8.4.6
Soft Start / Tracking (SS/TR)
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Programming the Output Voltage
9.2.2.2
Feedforward Capacitor
9.2.2.3
Input Capacitor
9.2.2.4
Output Capacitor
9.2.2.5
Application Curves
9.3
System Examples
9.3.1
Voltage Tracking
9.3.2
Synchronizing to an External Clock
9.4
Power Supply Recommendations
9.5
Layout
9.5.1
Layout Guidelines
9.5.2
Layout Example
9.5.2.1
Thermal Consideration
10
Device and Documentation Support
10.1
Device Support
10.1.1
サード・パーティ製品に関する免責事項
10.2
Documentation Support
10.2.1
Related Documentation
10.3
ドキュメントの更新通知を受け取る方法
10.4
サポート・リソース
10.5
Trademarks
10.6
静電気放電に関する注意事項
10.7
用語集
11
Revision History
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RDY|9
MPQF702B
サーマルパッド・メカニカル・データ
発注情報
jajsp69_oa
9.2.2
Detailed Design Procedure