JAJSP69 November   2023 TPSM828510 , TPSM828511 , TPSM828512

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Schematic
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Precise Enable (EN)
      2. 8.3.2 MODE/SYNC
      3. 8.3.3 Undervoltage Lockout (UVLO)
      4. 8.3.4 Power-Good Output (PG)
      5. 8.3.5 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pulse Width Modulation (PWM) Operation
      2. 8.4.2 Power Save Mode Operation (PFM/PWM)
      3. 8.4.3 100% Duty-Cycle Operation
      4. 8.4.4 Current Limit and Short-Circuit Protection
      5. 8.4.5 Output Discharge
      6. 8.4.6 Soft Start / Tracking (SS/TR)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Programming the Output Voltage
        2. 9.2.2.2 Feedforward Capacitor
        3. 9.2.2.3 Input Capacitor
        4. 9.2.2.4 Output Capacitor
        5. 9.2.2.5 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Voltage Tracking
      2. 9.3.2 Synchronizing to an External Clock
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
        1. 9.5.2.1 Thermal Consideration
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Over operating junction remperature range (TJ = -40°C to +125°C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ = 25°C. (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Quiescent current EN = VIN, no load, device not switching, MODE = GND, VOUT = 0.6 V 20 32 μA
ISD Shutdown current EN = GND, typical value at TJ = 25°C, maximum value at TJ = 125°C 1.5 18 μA
VUVLO Undervoltage lock out threshold VIN rising 2.45 2.6 2.7 V
VIN falling 2.1 2.5 2.6 V
TJSD Thermal shutdown threshold TJ rising 170 °C
Thermal shutdown hysteresis TJ falling 15 °C
CONTROL and INTERFACE
VEN,IH Input threshold voltage at EN, rising edge 1.05 1.1 1.15 V
VEN,IL Input threshold voltage at EN, falling edge 0.96 1.0 1.05 V
VIH High-level input-threshold voltage at MODE/SYNC 1.1 V
IEN,LKG Input leakage current into EN VIH = VIN or VIL = GND 125 nA
VIL Low-level input-threshold voltage at MODE/SYNC 0.3 V
ILKG Input leakage current into MODE/SYNC 100 nA
tDelay Enable delay time Time from EN high to device starts switching; VIN applied already 85 150 470 µs
tRamp Output voltage ramp time, CSS = 4.7 nF Time from device starts switching to power good; device not in current limit 0.8 1.3 1.8 ms
tRamp Output voltage ramp time, SS/TR pin open Time from device starts switching to power good; device not in current limit 90 150 210 µs
ISS/TR SS/TR source current 2 2.5 2.8 uA
Tracking gain VFB / VSS/TR 1
Tracking offset VFB when VSS/TR = 0 V ±1 mV
fSYNC Frequency range on MODE/SYNC pin for synchronization 1.8 4 MHz
Duty cycle of synchronization signal at MODE/SYNC 20 80 %
Time to lock to external frequency 50 µs
VTH_PG UVP power good threshold voltage;
DC level		 rising (%VFB) 92 95 98 %
VTH_PG UVP power good threshold voltage;
DC level		 falling (%VFB) 87 90 93 %
VTH_PG OVP power good threshold voltage;
DC level		 rising (%VFB) 107 110 113 %
OVP power good threshold voltage;
DC level		 falling (%VFB) 104 107 111 %
VPG,OL Low-level output voltage at PG ISINK_PG = 2 mA 0.07 0.3 V
IPG,LKG Input leakage current into PG VPG = 5 V 100 nA
tPG PG deglitch time for a high level to low level transition on the power good output 40 µs
OUTPUT
VFB Feedback voltage, adjustable version 0.6 V
IFB,LKG Input leakage current into FB, adjustable version VFB = 0.6 V 1 70 nA
VFB Feedback voltage accuracy PWM, VIN ≥ VOUT + 1 V –1 1 %
VFB Feedback voltage accuracy PFM, VIN ≥ VOUT + 1 V, VOUT ≥ 1.0 V, Co,eff ≥ 10 µF –1 2 %
VFB Feedback voltage accuracy PFM, VIN ≥ VOUT + 1 V, VOUT < 1.0 V, Co,eff ≥ 15 µF
 		 –1 3 %
VFB Feedback voltage accuracy with voltage tracking VIN ≥ VOUT + 1 V, VSS/TR = 0.3 V –4 4 %
Load regulation PWM 0.05 %/A
Line regulation PWM, IOUT = 1 A, VIN ≥ VOUT + 1 V 0.02 %/V
RDIS Output discharge resistance 100 Ω
fSW PWM Switching frequency 2.025 2.25 2.475 MHz
ton,min Minimum on-time of high-side FET VIN = 3.3 V, TJ = -40°C to 125°C 35 52 ns
ton,min Minimum on-time of low-side FET 10 ns
RDP Dropout resistance VIN ≥ 5 V
 		 85 120 mΩ
ILIMH High-side FET switch current limit DC value, for TPSM828512;
VIN = 3 V to 6 V		 2.85 3.4 3.9 A
ILIMH High-side FET switch current limit DC value, for TPSM828511;
VIN = 3 V to 6 V		 2.1 2.6 3.0 A
ILIMH High-side FET switch current limit DC value, for TPSM828510;
VIN = 3 V to 6 V		 1.6 2.1 2.5 A
ILIMNEG Low-side FET negative current limit DC value –1.8 A