JAJSTA1 August   2024 TPSM8287A12M , TPSM8287A15M

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency DCS-Control Topology
      2. 7.3.2  Forced-PWM and Power Save Modes
      3. 7.3.3  Precise Enable
      4. 7.3.4  Start-Up
      5. 7.3.5  Switching Frequency Selection
      6. 7.3.6  Output Voltage Setting
        1. 7.3.6.1 Output Voltage Setpoint
        2. 7.3.6.2 Output Voltage Range
        3. 7.3.6.3 Non-Default Output Voltage Setpoint
        4. 7.3.6.4 Dynamic Voltage Scaling (DVS)
      7. 7.3.7  Compensation (COMP)
      8. 7.3.8  Mode Selection / Clock Synchronization (MODE/SYNC)
      9. 7.3.9  Spread Spectrum Clocking (SSC)
      10. 7.3.10 Output Discharge
      11. 7.3.11 Undervoltage Lockout (UVLO)
      12. 7.3.12 Overvoltage Lockout (OVLO)
      13. 7.3.13 Overcurrent Protection
        1. 7.3.13.1 Cycle-by-Cycle Current Limiting
        2. 7.3.13.2 Hiccup Mode
        3. 7.3.13.3 Current-Limit Mode
      14. 7.3.14 Power Good (PG)
        1. 7.3.14.1 Power-Good Standalone, Primary Device Behavior
        2. 7.3.14.2 Power-Good Secondary Device Behavior
      15. 7.3.15 Remote Sense
      16. 7.3.16 Thermal Warning and Shutdown
      17. 7.3.17 Stacked Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset (POR)
      2. 7.4.2 Undervoltage Lockout
      3. 7.4.3 Standby
      4. 7.4.4 On
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 Standard-, Fast-, Fast-Mode Plus Protocol
      3. 7.5.3 I2C Update Sequence
      4. 7.5.4 I2C Register Reset
  9. 8 Device Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting the Input Capacitors
        2. 9.2.2.2 Selecting the Target Loop Bandwidth
        3. 9.2.2.3 Selecting the Compensation Resistor
        4. 9.2.2.4 Selecting the Output Capacitors
        5. 9.2.2.5 Selecting the Compensation Capacitor, CComp1
        6. 9.2.2.6 Selecting the Compensation Capacitor, CComp2
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application Using Four TPSM8287A1xM in Parallel Operation
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
        1. 9.3.2.1 Selecting the Input Capacitors
        2. 9.3.2.2 Selecting the Target Loop Bandwidth
        3. 9.3.2.3 Selecting the Compensation Resistor
        4. 9.3.2.4 Selecting the Output Capacitors
        5. 9.3.2.5 Selecting the Compensation Capacitor, CComp1
        6. 9.3.2.6 Selecting the Compensation Capacitor, CComp2
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2.4 Selecting the Output Capacitors

In practice, the total output capacitance is typically comprised of a combination of different capacitors, in which larger capacitors provide the load current at lower frequencies and smaller capacitors provide the load current at higher frequencies to satisfy the load impedance requirements. The value, type, and location of the output capacitors are typically defined by the load. TI recommends X7R multilayer ceramic capacitors (MLCCs) for best filtering and must be placed between both VOUT and GND pins, as close as possible to those pins. For applications with ambient temperatures below 85°C, capacitors with an X5R dielectric can be used. Ceramic capacitors have a DC-Bias effect, which has a strong influence on the final effective capacitance. Choose the right capacitors carefully in combination with considering the package size and voltage rating. The below calculations use the effective value of the total output capacitance.

The TPSM8287A1xM devices feature a butterfly or parallel layout with VOUT and GND pins on opposite sides of the package. This feature allows the output capacitors to be placed symmetrically on the PCB such that the electromagnetic fields cancel each other out, thereby reducing EMI.

The TPSM8287A1xM device is optimized to support harsh load transients. The device external loop compensation tunes the loop response to the desired response with a given output capacitance. The below calculations create designs that meet the load step specified in Table 9-2. These calculations typically result in total output capacitances of several hundred µF.

Best output voltage regulation is achieved when the TPSM8287A1xM device, the output capacitors, and load are placed very close to each other, keeping the distance and added inductance between the device and load to the absolute minimum.

In case this placement can not be achieved, then the majority of the total capacitance must be located at the load, with just two capacitors located at the TPSM8287A1xM device. TI recommends that the capacitance located at the load be at least twice the amount of the capacitance located at the device.

If the application does not contain harsh load transients, then smaller values of output capacitances are possible. Do not use output capacitances below the minimum values in Recommended Operating Conditions.

The transient response of the converter is defined by one of two criteria:

  • The slew rate of the current through the inductor, in which case the feedback loop of the converter saturates.
  • The loop bandwidth, in which the converter stays in regulation, and the loop does not saturate (BWτ < fSW / 4)
Which of the above criteria applies in any given application depends on the operating conditions and component values used. Calculate the output capacitance for both cases and select the higher of the two values.

If the converter remains in regulation, the minimum required output capacitance is given by:

Equation 17. COUT(min)(reg)=τ×1+gm×RComp12×π×LNɸ×BWτ1+TOLτ2+TOLIND2+TOLfSW2
Equation 18. COUT(min)(reg)=12.5×10–6×1+1.5×10–3×8062×π×100×10–91×300×1031+30%2+20%2+10%2=201.3μF

If the converter loop saturates, the minimum output capacitance is given by:

Equation 19. COUT(min)(sat)=1∆VOUTL×∆IOUT(max)22×VOUT×Nɸ – ∆IOUT(step)×tt21+TOLIND
Equation 20. COUT(min)(sat)=127×10–3100×10–9×9.722×0.9×1 – 8.0×1×10–621+20%=54.5μF

In this case, choose COUT(min) = 201.3µF as the larger of the two values for the output capacitance.

Table 9-3 lists the three output capacitors chosen. 2 × 47µF capacitors are placed close to the IC, giving a minimum effective capacitance of about 27µF each. A single 220µF capacitor is placed near the load to approximate the total decoupling capacitance required by a typical load. This 220µF capacitor yields about 138µF of effective capacitance. Together, the 192µF of effective capacitance is very close to the required minimum value calculated above. For further calculations, use COUT = 192µF.

Equation 21 checks that most of the output capacitance is placed at the load. If the ratio is less than 1, increase the capacitance at the load or place the device, output capacitance, and load next to each other such that there is no separation between the output capacitances.

Equation 21. C LOAD 2 × C OUT > 1
Equation 22.   138   ×   10 - 6   2   × ( 2 × 27 ×   10 - 6 ) > 1 = True

Equation 23 calculates the output voltage ripple, based on the effective output capacitance value.

Equation 23. VOUT(p-p)=IL(PP)8×COUT×fsw
Equation 24. VOUT(p-p)=3.48×192×10-6×2.25×106 =0.984 mV

The ripple is slightly higher in the application, due to the ESR and ESL in the output capacitors and the application board parasitics.