JAJSTA1 August   2024 TPSM8287A12M , TPSM8287A15M

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency DCS-Control Topology
      2. 7.3.2  Forced-PWM and Power Save Modes
      3. 7.3.3  Precise Enable
      4. 7.3.4  Start-Up
      5. 7.3.5  Switching Frequency Selection
      6. 7.3.6  Output Voltage Setting
        1. 7.3.6.1 Output Voltage Setpoint
        2. 7.3.6.2 Output Voltage Range
        3. 7.3.6.3 Non-Default Output Voltage Setpoint
        4. 7.3.6.4 Dynamic Voltage Scaling (DVS)
      7. 7.3.7  Compensation (COMP)
      8. 7.3.8  Mode Selection / Clock Synchronization (MODE/SYNC)
      9. 7.3.9  Spread Spectrum Clocking (SSC)
      10. 7.3.10 Output Discharge
      11. 7.3.11 Undervoltage Lockout (UVLO)
      12. 7.3.12 Overvoltage Lockout (OVLO)
      13. 7.3.13 Overcurrent Protection
        1. 7.3.13.1 Cycle-by-Cycle Current Limiting
        2. 7.3.13.2 Hiccup Mode
        3. 7.3.13.3 Current-Limit Mode
      14. 7.3.14 Power Good (PG)
        1. 7.3.14.1 Power-Good Standalone, Primary Device Behavior
        2. 7.3.14.2 Power-Good Secondary Device Behavior
      15. 7.3.15 Remote Sense
      16. 7.3.16 Thermal Warning and Shutdown
      17. 7.3.17 Stacked Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset (POR)
      2. 7.4.2 Undervoltage Lockout
      3. 7.4.3 Standby
      4. 7.4.4 On
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 Standard-, Fast-, Fast-Mode Plus Protocol
      3. 7.5.3 I2C Update Sequence
      4. 7.5.4 I2C Register Reset
  9. 8 Device Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting the Input Capacitors
        2. 9.2.2.2 Selecting the Target Loop Bandwidth
        3. 9.2.2.3 Selecting the Compensation Resistor
        4. 9.2.2.4 Selecting the Output Capacitors
        5. 9.2.2.5 Selecting the Compensation Capacitor, CComp1
        6. 9.2.2.6 Selecting the Compensation Capacitor, CComp2
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application Using Four TPSM8287A1xM in Parallel Operation
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
        1. 9.3.2.1 Selecting the Input Capacitors
        2. 9.3.2.2 Selecting the Target Loop Bandwidth
        3. 9.3.2.3 Selecting the Compensation Resistor
        4. 9.3.2.4 Selecting the Output Capacitors
        5. 9.3.2.5 Selecting the Compensation Capacitor, CComp1
        6. 9.3.2.6 Selecting the Compensation Capacitor, CComp2
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.3 Precise Enable

The Enable (EN) pin is bidirectional and has two functions. See Figure 7-9:

  • As an input, the pin enables and disables the DC/DC converter in the device
  • In a stacked configuration, the pin is an output and provides a SYSTEM_READY signal to other devices.


TPSM8287A12M TPSM8287A15M Enable Functional Block Diagram

Figure 7-9 Enable Functional Block Diagram
Because there is an internal open-drain transistor connected to the EN pin, do not drive this pin directly from a low-impedance source. Instead, use a > 15kOhm resistor to limit the current flowing into the EN pin.

When power is first applied to the VIN pin, the device pulls the EN pin low until the pin loads the default register settings from nonvolatile memory and reads the state of the VSETx and SYNC_OUT pins. The device also pulls EN low if a fault, such as thermal shutdown or overvoltage lockout, occurs. In a stacked configuration, all devices share a common enable signal, which means that the DC/DC converters in the stack cannot start to switch until all devices in the stack have completed the initialization. Similarly, a fault in one or more devices in the stack disables all converters in the stack (see Section 7.3.17).

In standalone (non-stacked) applications, set SINGLE = 1 in the CONTROL3 register to disable the active pulldown of the EN pin. Fault conditions have no effect on the EN pin when SINGLE = 1. (Note that the EN pin is always pulled down during device initialization.) In stacked applications, make sure that SINGLE = 0. Setting SINGLE = 1 also disables the SYNC_OUT pin.

When the internal SYSTEM_READY signal is low (that is, initialization is complete and there are no fault conditions), the internal open-drain transistor is high impedance and the EN pin functions like a standard input: a high level on the EN pin enables the DC/DC converter in the device and a low level disables the DC/DC converter. The I2C interface is enabled as soon as the device has completed the initialization and is not affected by the state of the internal ENABLE or SYSTEM_READY signals.

A low level on the EN pin forces the device into shutdown. During shutdown, the MOSFETs in the power stage are off, the internal control circuitry is disabled, and the device consumes less than 20µA (typical). Do not leave the EN pin floating.

The Precise Enable input provides a user-programmable undervoltage lockout by adding a resistor divider to the input of the EN pin. The Precise Enable input also allows the user to drive the pin by a slowly changing voltage and enables the use of an external RC network to achieve a precise power-up delay. See Achieving a clean startup by using a DC/DC converter with a precise enable-pin threshold analog design journal for more details.