JAJSD30I May   2012  – March 2017 TRF7964A

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Characteristics
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Electrical Characteristics
    5. 5.5 Thermal Resistance Characteristics
    6. 5.6 Switching Characteristics
  6. 6Detailed Description
    1. 6.1  Overview
      1. 6.1.1 RFID - Reader and Writer
    2. 6.2  System Block Diagram
    3. 6.3  Power Supplies
      1. 6.3.1 Supply Arrangements
      2. 6.3.2 Supply Regulator Settings
      3. 6.3.3 Power Modes
    4. 6.4  Receiver - Analog Section
      1. 6.4.1 Main and Auxiliary Receivers
      2. 6.4.2 Receiver Gain and Filter Stages
    5. 6.5  Receiver - Digital Section
      1. 6.5.1 Received Signal Strength Indicator (RSSI)
        1. 6.5.1.1 Internal RSSI - Main and Auxiliary Receivers
        2. 6.5.1.2 External RSSI
    6. 6.6  Oscillator Section
    7. 6.7  Transmitter - Analog Section
    8. 6.8  Transmitter - Digital Section
    9. 6.9  Transmitter - External Power Amplifier and Subcarrier Detector
    10. 6.10 TRF7964A IC Communication Interface
      1. 6.10.1 General Introduction
        1. 6.10.1.1 Continuous Address Mode
        2. 6.10.1.2 Noncontinuous Address Mode (Single Address Mode)
        3. 6.10.1.3 Direct Command Mode
        4. 6.10.1.4 FIFO Operation
      2. 6.10.2 Parallel Interface Mode
      3. 6.10.3 Reception of Air Interface Data
      4. 6.10.4 Data Transmission From MCU to TRF7964A
      5. 6.10.5 Serial Interface Communication (SPI)
        1. 6.10.5.1 Serial Interface Mode With Slave Select (SS)
      6. 6.10.6 Direct Mode
    11. 6.11 TRF7964A Initialization
    12. 6.12 Special Direct Mode for Improved MIFARE Compatibility
    13. 6.13 Direct Commands from MCU to Reader
      1. 6.13.1 Command Codes
        1. 6.13.1.1  Idle (0x00)
        2. 6.13.1.2  Software Initialization (0x03)
        3. 6.13.1.3  Reset FIFO (0x0F)
        4. 6.13.1.4  Transmission With CRC (0x11)
        5. 6.13.1.5  Transmission Without CRC (0x10)
        6. 6.13.1.6  Delayed Transmission With CRC (0x13)
        7. 6.13.1.7  Delayed Transmission Without CRC (0x12)
        8. 6.13.1.8  Transmit Next Time Slot (0x14)
        9. 6.13.1.9  Block Receiver (0x16)
        10. 6.13.1.10 Enable Receiver (0x17)
        11. 6.13.1.11 Test Internal RF (RSSI at RX Input With TX ON) (0x18)
        12. 6.13.1.12 Test External RF (RSSI at RX Input with TX OFF) (0x19)
    14. 6.14 Register Description
      1. 6.14.1 Register Preset
      2. 6.14.2 Register Overview
      3. 6.14.3 Detailed Register Description
        1. 6.14.3.1 Main Configuration Registers
          1. 6.14.3.1.1 Chip Status Control Register (0x00)
          2. 6.14.3.1.2 ISO Control Register (0x01)
        2. 6.14.3.2 Control Registers - Sublevel Configuration Registers
          1. 6.14.3.2.1  ISO/IEC 14443 TX Options Register (0x02)
          2. 6.14.3.2.2  ISO/IEC 14443 High-Bit-Rate and Parity Options Register (0x03)
          3. 6.14.3.2.3  TX Timer High Byte Control Register (0x04)
          4. 6.14.3.2.4  TX Timer Low Byte Control Register (0x05)
          5. 6.14.3.2.5  TX Pulse Length Control Register (0x06)
          6. 6.14.3.2.6  RX No Response Wait Time Register (0x07)
          7. 6.14.3.2.7  RX Wait Time Register (0x08)
          8. 6.14.3.2.8  Modulator and SYS_CLK Control Register (0x09)
          9. 6.14.3.2.9  RX Special Setting Register (0x0A)
          10. 6.14.3.2.10 Regulator and I/O Control Register (0x0B)
        3. 6.14.3.3 Status Registers
          1. 6.14.3.3.1 IRQ Status Register (0x0C)
          2. 6.14.3.3.2 Interrupt Mask Register (0x0D) and Collision Position Register (0x0E)
          3. 6.14.3.3.3 RSSI Levels and Oscillator Status Register (0x0F)
          4. 6.14.3.3.4 Special Functions Register (0x10)
          5. 6.14.3.3.5 Special Functions Register (0x11)
          6. 6.14.3.3.6 Adjustable FIFO IRQ Levels Register (0x14)
        4. 6.14.3.4 Test Registers
          1. 6.14.3.4.1 Test Register (0x1A)
          2. 6.14.3.4.2 Test Register (0x1B)
        5. 6.14.3.5 FIFO Control Registers
          1. 6.14.3.5.1 FIFO Status Register (0x1C)
          2. 6.14.3.5.2 TX Length Byte1 Register (0x1D), TX Length Byte2 Register (0x1E)
  7. 7Applications, Implementation, and Layout
    1. 7.1 TRF7964A Reader System Using SPI With SS Mode
      1. 7.1.1 General Application Considerations
      2. 7.1.2 Schematic
    2. 7.2 Layout Considerations
    3. 7.3 Impedance Matching TX_Out (Pin 5) to 50 Ω
    4. 7.4 Reader Antenna Design Guidelines
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 使い始めと次の手順
    2. 8.2 デバイスの項目表記
    3. 8.3 ツールとソフトウェア
    4. 8.4 ドキュメントのサポート
    5. 8.5 コミュニティ・リソース
    6. 8.6 商標
    7. 8.7 静電気放電に関する注意事項
    8. 8.8 Glossary
  9. 9メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

2 改訂履歴

Changes from April 18, 2014 to March 27, 2017

  • Section 1.3、「概要」の内容を変更Go
  • Added Section 3.1, Related Products Go
  • Moved TSTG from Section 5.2 to Section 5.1, Absolute Maximum RatingsGo
  • Added VOL and VOH to Section 5.4, Electrical Characteristics Go
  • Changed the TYP value of the fD_CLKmax parameter from 8 to 4 MHz in Section 5.4, Electrical Characteristics Go
  • Throughout document, removed support for application control of Automatic Gain Control (AGC) and Receiver Gain Adjust, because these features were designed for test functionality and not for production useGo
  • Added the sentence that starts "For applications in which the TRF7964A may be subjected..." in the second paragraph of Section 6.3, Power SuppliesGo
  • Changed VDD_A to VDD_X in the last sentence that reads "The VDD_X output current should not exceed 20 mA." in the NOTE in Analog Supply Regulator: VDD_AGo
  • Removed the paragraph that started "The RF power amplifier regulator..." from Digital Supply Regulator: VDD_X Go
  • Added the paragraph that starts "As VDD_RF is increased, the system..." in Section 6.3.2, Supply Regulator Settings Go
  • Removed the paragraphs that started "The main receiver also has..." and "By default, the AGC window comparator..." from Section 6.4.2, Receiver Gain and Filter Stages Go
  • Changed Table 6-5 to match Table 6-31Go
  • Updated Section 6.5, Receiver – Digital Section, to clarify and remove duplicate contentGo
  • Updated the description in Section 6.5.1.2, External RSSIGo
  • Removed "Equivalent Series Resistance" from Table 6-8, Minimum Crystal RecommendationsGo
  • Removed mention of 3-wire SPI and replaced "IRQ" with "Slave Select" in the first paragraph of Section 6.10.1, General IntroductionGo
  • Updated the description of FIFO level interrupts in Section 6.10.1.4, FIFO OperationGo
  • Added "but recommended" to "It is optional but recommended to read the FIFO Status register..." in Section 6.10.3, Reception of Air Interface DataGo
  • Changed the title of Section 6.10.4, Data Transmission From MCU to TRF7964AGo
  • Removed the sentence that started "The choice of one of these modes over another..." from Section 6.10.5, Serial Interface Communication (SPI)Go
  • Updated the paragraph that starts "TI recommends resetting the FIFO after receiving data..." in Section 6.10.5.1, Serial Interface Mode With Slave Select (SS)Go
  • Added the NOTE that starts "An additional direct mode..." in Section 6.10.6, Direct ModeGo
  • Added Section 6.11, TRF7964A Initialization Go
  • Changed the application report that is referenced in Section 6.12, Special Direct Mode for Improved MIFARE™ CompatibilityGo
  • Added and updated comments in Table 6-14, Address and Command Word Bit DistributionGo
  • Removed unsupported registers (addresses 0x15 to 0x19) in Table 6-16, Register Values After Sending Software Initialization (0x03)Go
  • Added "This is used by the ISO/IEC 15693 protocol" to Section 6.13.1.8, Transmit Next Time Slot (0x14)Go
  • Corrected description of B1 Irq_col in Table 6-37, IRQ Status Register (0x0C): changed from "(as defined in register 0x01)" to "(as defined in register 0x10)" Go
  • Changed the description of B5:B3 in Table 6-40 from "...Auxiliary RSSI represents the signal level at RX_IN2" to "...Auxiliary RSSI represents the signal level at RX_IN1"Go
  • Updated the description in Section 7.1.2, SchematicGo
  • Section 8.1、「使い始めと次の手順」を追加Go
  • Section 8.2、「デバイスの項目表記」を追加Go
  • Section 8.3、「ツールとソフトウェア」を追加Go
  • Section 8.4、「ドキュメントのサポート」を更新Go