| PACKAGE |
θJA |
θJC |
| J-16 |
80-120 |
28(2) |
| N-16 |
90(1) |
45 |
| DW-16 |
45-90(1) |
25 |
| PLCC-20 (Q package) |
43-75(1) |
34 |
| LCC-20 (L package) |
70-80 |
20(2) |
(1) Specified θJA (junction to ambient) is for devices
mounted to 5 in2 FR4 PC board with one ounce copper where noted. When resistance
range is given, lower values are for 5 in2 aluminum PC board. Test PWB was
0.062" thick and typically used 0.635 mm trace widths for power packages and 1.3
mm trace widths for non-power packages with 100 x 100 mil probe land area at the
end of each trace.
(2) θJC data values stated were derived from MIL-STD-1835B.
MIL-STD-1835B states, "The baseline values shown are worst case (mean + 2s) for
a 60 x 60 mil microcircuit device silicon die and applicable for devices with
die sizes up to 14400 square mils. For device die size greater than 14400 square
mils use the following values; dual-in-line, 11°C/W; flat pack, 10°C/W; pin grid
array, 10°C/W".