JAJSP14F August   1995  – August 2022 UC1823A , UC1825A , UC2823A , UC2823B , UC2825A , UC2825B , UC3823A , UC3823B , UC3825A , UC3825B

PRODUCTION DATA  

  1. 1特長
  2. 2概要
  3. 3Revision History
  4. 4Ordering Information
  5. 5Pin Configuration and Functions
    1.     Terminal Functions
  6. 6Specifications
    1. 6.1 ABSOLUTE MAXIMUM RATINGS
    2. 6.2 Thermal Information
    3. 6.3 ELECTRICAL CHARACTERISTICS
    4. 6.4 ELECTRICAL CHARACTERISTICS
  7. 7Application and Implementation
    1. 7.1 LEADING EDGE BLANKING
    2. 7.2 UVLO、ソフト・スタート、フォルト管理
    3. 7.3 ACTIVE LOW OUTPUTS DURING UVLO
    4. 7.4 CONTROL METHODS
    5. 7.5 SYNCHRONIZATION
    6. 7.6 HIGH CURRENT OUTPUTS
    7. 7.7 GROUND PLANES
    8. 7.8 OPEN LOOP TEST CIRCUIT
  8. 8Device and Documentation Support
    1. 8.1 Documentation Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DW|16
サーマルパッド・メカニカル・データ
発注情報

6.3 ELECTRICAL CHARACTERISTICS

TA = –55°C to 125°C for the UC1823A/UC1825A, TA = –40°C to 85°C for the UC2823x/UC2825x, TA = 0°C to 70°C for the UC3823x/UC3825x, RT = 3.65 kΩ, CT = 1 nF, VCC = 12 V, TA = TJ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REFERENCE, VREF
VO Ouput voltage range TJ = 25°C, IO = 1 mA 5.05 5.1 5.15 V
Line regulation 12 V ≤ VCC ≤ 20 V 2 15 mV
Load regulation 1 mA ≤ IO ≤ 10 mA 5 20
Total output variation Line, load, temperature 5.03 5.17 V
Temperature stability(1) T(min) < TA < T(max) 0.2 0.4 mV/°C
Output noise voltage(1) 10 Hz < f < 10 kHz 50 μVRMS
Long term stability(1) TJ = 125°C, 1000 hours 5 25 mV
Short circuit current VREF = 0 V 30 60 90 mA
OSCILLATOR
fOSC Initial accuracy(1) TJ = 25°C 375 400 425 kHz
RT = 6.6 kΩ, CT = 220 pF, TA = 25°C 0.9 1 1.1 MHz
Total variation(1) Line, temperature 350 450 kHz
RT = 6.6 kΩ, CT = 220 pF 0.85 1.15 MHz
Voltage stability 12 V < VCC < 20 V 1%
Temperature stability(1) T(min) < TA < T(max) ±5%
High-level output voltage, clock 3.7 4 V
Low-level output voltage, clock 0 0.2
Ramp peak 2.6 2.8 3
Ramp valley 0.7 1 1.25
Ramp valley-to-peak 1.6 1.8 2
IOSC Oscillator discharge current RT = OPEN, VCT = 2 V 9 10 11 mA
ERROR AMPLIFIER
Input offset voltage 2 10 mV
Input bias current 0.6 3 μA
Input offset current 0.1 1
Open loop gain 1 V < VO < 4 V 60 95 dB
CMRR Common mode rejection ratio 1.5 V < VCM < 5.5 V 75 95
PSRR Power supply rejection ratio 12 V < VCC < 20 V 85 110
IO(sink) Output sink current VEAOUT = 1 V 1 2.5 mA
IO(src) Output source current VEAOUT = 4 V –1.3 –0.5
High-level output voltage IEAOUT = –0.5 mA 4.5 4.7 5 V
Low-level output voltage IEAOUT = –1 mA 0 0.5 1
Gain bandwidth product f = 200 kHz 6 12 Mhz
Slew rate(1) 6 9 V/μs
(1) Ensured by design. Not production tested.