JAJSHM6E june   2019  – february 2021 UCC256402 , UCC256403 , UCC256404

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6.   Device Comparison Table
  7. 5 Pin Configuration and Functions
    1.     Pin Functions
  8. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Hybrid Hysteretic Control
      2. 7.3.2 Regulated 13-V Supply
      3. 7.3.3 Feedback Chain
        1. 7.3.3.1 Optocoupler Feedback Signal Input and Bias
        2. 7.3.3.2 FB Pin Voltage Clamp
        3. 7.3.3.3 "Pick Lower Value" Block and Soft Start Multiplexer
        4. 7.3.3.4 Pick Higher Block and Burst Mode Multiplexer
        5. 7.3.3.5 VCR Comparators
      4. 7.3.4 Resonant Capacitor Voltage Sensing
      5. 7.3.5 Resonant Current Sensing
      6. 7.3.6 Bulk Voltage Sensing
      7. 7.3.7 Output Voltage Sensing
      8. 7.3.8 High Voltage Gate Driver
        1. 7.3.8.1 Adaptive Dead Time Control
      9. 7.3.9 Protections
        1. 7.3.9.1 ZCS Region Prevention
        2. 7.3.9.2 Over Current Protection (OCP)
        3. 7.3.9.3 Bias Winding Over Voltage Protection (BWOVP)
        4. 7.3.9.4 Input Under Voltage Protection (VINUVP)
        5. 7.3.9.5 Input Over Voltage Protection (VINOVP)
        6. 7.3.9.6 Boot UVLO
        7. 7.3.9.7 RVCC UVLO
        8. 7.3.9.8 Over Temperature Protection (OTP)
    4. 7.4 Device Functional Modes
      1. 7.4.1 High Voltage Start-Up
      2. 7.4.2 X-Capacitor Discharge
      3. 7.4.3 Burst Mode Control
        1. 7.4.3.1 Soft-Start and Burst-Mode Threshold
        2. 7.4.3.2 BMTL/BMTH Ratio Programming
      4. 7.4.4 System State Machine
  10.   Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  LLC Power Stage Requirements
        2. 8.2.2.2  LLC Gain Range
        3. 8.2.2.3  Select Ln and Qe
        4. 8.2.2.4  Determine Equivalent Load Resistance
        5. 8.2.2.5  Determine Component Parameters for LLC Resonant Circuit
        6. 8.2.2.6  LLC Primary-Side Currents
        7. 8.2.2.7  LLC Secondary-Side Currents
        8. 8.2.2.8  LLC Transformer
        9. 8.2.2.9  LLC Resonant Inductor
        10. 8.2.2.10 LLC Resonant Capacitor
        11. 8.2.2.11 LLC Primary-Side MOSFETs
        12. 8.2.2.12 LLC Rectifier Diodes
        13. 8.2.2.13 LLC Output Capacitors
        14. 8.2.2.14 HV Pin Series Resistors
        15. 8.2.2.15 BLK Pin Voltage Divider
        16. 8.2.2.16 ISNS Pin Differentiator
        17. 8.2.2.17 VCR Pin Capacitor Divider
        18. 8.2.2.18 BW Pin Voltage Divider
        19. 8.2.2.19 Soft Start and Burst Mode Programming
      3. 8.2.3 Application Curves
  11. 8 Power Supply Recommendations
    1. 8.1 VCC Pin Capacitor
    2. 8.2 Boot Capacitor
    3. 8.3 RVCC Pin Capacitor
  12. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  13. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Related Links
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
  14.   Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4.4 System State Machine

Below is an overview of the system states sequence:

The state transition diagram starts from the un-powered condition of UCC25640x. For device variants that has HV startup, as soon as the AC input is plugged in, the internal JFET of the HV pin will be enabled and will start to deliver current from a source connected from the HV pin to the VCC capacitor. Once the VCC pin voltage exceeds its VCCStartSwitching threshold, the system state will change to JFETOFF. For device variants which does not have HV startup feature, there is no JFETon state. Once VCC exceeds its VCCStartSwitching threshold, the system state will change to JFETOFF. When the PFC output voltage reaches a certain level, the LLC is turned on. Before the LLC starts running, the LO pin is kept high to pull the HS node of the LLC bridge low, thus allowing the capacitor between the HB and HS pins to be charged from VCC via the bootstrap diode. UCC25640x will remain in the CHARGE_BOOT state for a certain time to ensure the boot capacitor is fully charged. When the LLC output voltage reaches a certain level, both PFC and LLC controllers get power from the LLC transformer bias winding. When the load drops below a certain level, the LLC operates in burst mode.

Fault conditions encountered by UCC25640x will cause normal operation to stop, or pause for a certain period of time followed by an automatic re-start. This is to ensure that while a persistent fault condition is present, it is not possible for the temperature of UCC25640x controller or the power converter to rise as a result of the repeated re-start attempts.

GUID-5F0A7FB9-1242-4D9D-BADA-DCAB25C6679B-low.gifFigure 7-21 Block Diagram of System State Machine

Table 7-3 summarizes the inputs and outputs of Figure 7-21.

Table 7-3 System State Machine Block Inputs and Outputs
SIGNAL NAMEI/ODESCRIPTION
BWOVPIOutput over voltage fault
OTPIOver temperature fault
OCP1IPeak current fault
OCP2IAverage current fault with 2 ms timer
OCP3IAverage current fault with 50 ms timer
BLKStartIBulk voltage is above start threshold
BLKStopIBulk voltage is below stop threshold
RVCCUVLOIRVCC UVLO fault
VCCReStartJfetIVCC is below restart threshold
VCCStartSwitchingIVCC is above start switching threshold
ACZeroCrossingIAC zero crossing is detected
WaveGenEnOWaveform generator enable
RVCCEnORVCC enable
SSEnOSoft start enable
HVFetOnOTurn on or off JFET

The state machine is shown in Figure 7-22 and the description of the states and state transition conditions are in the tables below.

GUID-1377B834-0F7B-417E-9611-C8FFBF22A39D-low.gifFigure 7-22 System State Machine Transition
Table 7-4 States in System State Machine
STATEOUTPUT STATUSDESCRIPTION
STARTUPWaveGenEn = 0
RVCCEn = 0
SSEn = 0
HVFetOn = 0		This is the first state after AC input is plugged-in for the system to load trim.
JFETONWaveGenEn = 0
RVCCEn = 0
SSEn = 0
HVFetOn = 1		In this state, the JFET is on. VCC is charged with a current source connected from HV pin. For device variants that does not have HV startup feature, this state does not exist.
JFETOFFWaveGenEn = 0
RVCCEn = 1
SSEn = 0
HVFetOn = 0		When VCC is higher than VCCStartSwitching threshold, the JFET is turned off and the system enters JFETOFF state. The regulated RVCC is turned on. If RVCC is supplied to PFC voltage supply pin, PFC soft start begins.
WAKEUPWaveGenEn = 0
RVCCEn = 1
SSEn = 0
HVFetOn = 0		When BLK voltage reaches BLKStart level, the system enters WAKEUP state and stays in WAKEUP state for a short time for the analog circuits to wake up.
LLSS/BW ProgrammingWaveGenEn = 0
RVCCEn = 1
SSEn = 0
HVFetOn = 0		In this state, the system goes through the LL/SS pin and BW pin programming phase.
CHARGE_BOOTWaveGenEn = 0
RVCCEn = 1
SSEn = 0
HVFetOn = 0		In this state, the BOOT capacitor is charged by turning on the low-side switch for a certain period of time. The programmed initial voltage is buffered to LL/SS pin.
STEADY_STATE_RUNWaveGenEn = 1
RVCCEn = 1
SSEn = 1
HVFetOn = 0		In this state, the waveform generator is enabled. Soft start module is enabled. The LLC starts to soft start. When soft start is done, the system enters normal operation.
FAULTWaveGenEn = 0
RVCCEn = 0
SSEn = 0
HVFetOn = 0		In fault state, the waveform generator is disabled to stop switching. The system will stay in FAULT state for 1 s before re-start. The 1 s timer allows the system to cool down and prevents frequent repetitive start ups in case of a persistent fault.
Table 7-5 System State Machine Transition Conditions
STATE TRANSITION CONDITIONDESCRIPTION
1System ready (trim load done)
2VCCStartSwitching = 1
VCCReStartJfet = 0
3BLKStart = 1
BLKStop = 0
RVCCUVLO = 0
4BLKStart = 1
BLKStop = 0
RVCCUVLO = 0
FBLessThanBMT = 0
5LLSS/BW programming done
6Charge boot done
7VCCReStartJfet = 1
8VCCReStartJfet = 1
9VCCReStartJfet = 1
10VCCReStartJfet = 1
11VCCReStartJfet = 1
12OTP = 1
13OTP = 1
14OTP = 1
15OTP = 1
16OTP = 1
17OTP = 1 or BLKStop = 1 or BWOVP = 1 or
OCP1 = 1 or OCP 2 = 1 or OCP3 = 1 or
RVCCUVLO = 1
181 s pause time out

Figure 7-23 and Figure 7-24 show the most commonly used state transition (assuming no faults during start up states so all the states are captured in the timing diagram). Many different ways of state transitions may happen according to the state machine, but are not captured in this section.

In Figure 7-24, a normal start up procedure is shown. The system enters normal operation and then a fault (OCP, OVP, or OTP) happens.

GUID-760CE813-4310-453F-B856-77F1681BE4D3-low.gifFigure 7-23 Timing Diagram of System State Machine for UCC256403
GUID-A32722B1-D9EF-495D-8A8A-9ACE11B5AAC8-low.gifFigure 7-24 Timing Diagram of System State Machine for UCC256402 and UCC256404