SGLS121D December   2002  – June 2020 UCC2800-Q1 , UCC2801-Q1 , UCC2802-Q1 , UCC2803-Q1 , UCC2804-Q1 , UCC2805-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application Diagram
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Detailed Pin Description
        1. 9.3.1.1 COMP
        2. 9.3.1.2 FB
        3. 9.3.1.3 CS
        4. 9.3.1.4 RC
        5. 9.3.1.5 GND
        6. 9.3.1.6 OUT
        7. 9.3.1.7 VCC
        8. 9.3.1.8 Pin 8 (REF)
      2. 9.3.2  Undervoltage Lockout (UVLO)
      3. 9.3.3  Self-Biasing, Active Low Output
      4. 9.3.4  Reference Voltage
      5. 9.3.5  Oscillator
      6. 9.3.6  Synchronization
      7. 9.3.7  PWM Generator
      8. 9.3.8  Minimum Off-Time Setting (Dead-Time Control)
      9. 9.3.9  Leading Edge Blanking
      10. 9.3.10 Minimum Pulse Width
      11. 9.3.11 Current Limiting
      12. 9.3.12 Overcurrent Protection and Full Cycle Restart
      13. 9.3.13 Soft Start
      14. 9.3.14 Slope Compensation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Operation
      2. 9.4.2 UVLO Mode
      3. 9.4.3 Soft Start Mode
      4. 9.4.4 Fault Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Current Sensing Network
        2. 10.2.2.2 Gate Drive Resistor
        3. 10.2.2.3 Vref Capacitor
        4. 10.2.2.4 RTCT
        5. 10.2.2.5 Start-Up Circuit
        6. 10.2.2.6 Voltage Feedback Compensation
          1. 10.2.2.6.1 Power Stage Gain, Zeroes, and Poles
          2. 10.2.2.6.2 Compensation Loop
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Community Resources
    2. 13.2 Trademarks
    3. 13.3 Related Links
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
サーマルパッド・メカニカル・データ
発注情報

10.2.3 Application Curves

UCC2800-Q1 UCC2801-Q1 UCC2802-Q1 UCC2803-Q1 UCC2804-Q1 UCC2805-Q1 PMP9275A 240Vac Drain Waveform1.pngFigure 38. Primary Side MOSFET Drain to Source Voltage at 240-V AC Input (100 V/div)
UCC2800-Q1 UCC2801-Q1 UCC2802-Q1 UCC2803-Q1 UCC2804-Q1 UCC2805-Q1 PMP9275A 120Vac 1-3A Step Resp1.pngFigure 40. Output Voltage During 0.9-A to 2.7-A Load Transient (CH1: Output Voltage AC Coupled, 200 mV/div; CH4: Output Current, 1 A/div)
UCC2800-Q1 UCC2801-Q1 UCC2802-Q1 UCC2803-Q1 UCC2804-Q1 UCC2805-Q1 PMP9275A naVac Start-up Full Load1.pngFigure 42. Output Voltage Behavior at Full Load Start-up (5 V/div)
UCC2800-Q1 UCC2801-Q1 UCC2802-Q1 UCC2803-Q1 UCC2804-Q1 UCC2805-Q1 PMP9275A 120Vac Drain Waveform1.pngFigure 39. Primary Side MOSFET Drain to Source Voltage at 120-V AC Input (100 V/div)
UCC2800-Q1 UCC2801-Q1 UCC2802-Q1 UCC2803-Q1 UCC2804-Q1 UCC2805-Q1 PMP9275A 120Vac Vripple Full Load1.pngFigure 41. Output Voltage Ripple at Full Load (100 mV/div)