SLUSB86C November   2012  – June 2017 UCC28710 , UCC28711 , UCC28712 , UCC28713

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Detailed Pin Description
        1. 8.3.1.1 VDD (Device Bias Voltage Supply)
        2. 8.3.1.2 GND (Ground)
        3. 8.3.1.3 VS (Voltage-Sense)
        4. 8.3.1.4 DRV (Gate Drive)
        5. 8.3.1.5 CS (Current Sense)
        6. 8.3.1.6 CBC (Cable Compensation), Pin 1 UCC28700
        7. 8.3.1.7 NTC (NTC Thermistor Shut-down), Pin 1 UCC28701/2/3
      2. 8.3.2 Fault Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Primary-Side Voltage Regulation
      2. 8.4.2 Primary-Side Current Regulation
      3. 8.4.3 Valley Switching
      4. 8.4.4 Start-Up Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Stand-by Power Estimate
        3. 9.2.2.3 Input Bulk Capacitance and Minimum Bulk Voltage
        4. 9.2.2.4 Transformer Turns Ratio, Inductance, Primary-Peak Current
        5. 9.2.2.5 Transformer Parameter Verification
        6. 9.2.2.6 Output Capacitance
        7. 9.2.2.7 VDD Capacitance, CDD
        8. 9.2.2.8 VS Resistor Divider, Line Compensation, and Cable Compensation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Custom Design With WEBENCH® Tools
      2. 12.1.2 Device Nomenclature
        1. 12.1.2.1  Capacitance Terms in Farads
        2. 12.1.2.2  Duty Cycle Terms
        3. 12.1.2.3  Frequency Terms in Hertz
        4. 12.1.2.4  Current Terms in Amperes
        5. 12.1.2.5  Current and Voltage Scaling Terms
        6. 12.1.2.6  Transformer Terms
        7. 12.1.2.7  Power Terms in Watts
        8. 12.1.2.8  Resistance Terms in Ω
        9. 12.1.2.9  Timing Terms in Seconds
        10. 12.1.2.10 Voltage Terms in Volts
        11. 12.1.2.11 AC Voltage Terms in VRMS
        12. 12.1.2.12 Efficiency Terms
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
      2. 12.2.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|7
サーマルパッド・メカニカル・データ
発注情報

11 Layout

11.1 Layout Guidelines

  • High frequency bypass Capacitor C5 should be placed across Pin 1 and 4 as close as you can get it to the pins.
  • Resistor R4 and C5 form a low pass filter and the connection of R4 and C5 should be as close to the VDD pin as possible.
  • The VS pin controls the output voltage through the transformer turns ratio and the voltage divider of R5 and R11. Note the trace length between the R5, R11 and VS pin should be as short as possible to reduce or eliminate possible EMI coupling.
  • Note the IC ground and power ground should meet at the bulk capacitor’s (C6 and C7) return. Try to ensure that high frequency/high current from the power stage does not go through the signal ground.
    • The high frequency/high current path that you need to be cautious of on the primary is C7 +, T1 (P5, P3), Q1d, Q1s, R8 to the return of C6 and C7. Try to keep all high current loops as short as possible.
  • Try to keep all high current loops as short as possible.
  • Keep all high current/high frequency traces away from or perpendicular to other traces in the design.
  • Traces on the voltage clamp formed by D1, R2, D3 and C2 as short as possible.
  • C6 return needs to be as close to the bulk capacitor supply as possible. This reduces the magnitude of dv/dt caused by large di/dt.
  • Avoid mounting semiconductors under magnetics.

UCC28710 UCC28711 UCC28712 UCC28713 swusbadapter.gif
No value means not populated.
Figure 29. 5-W USB Adapter Schematic

11.2 Layout Example

UCC28710 UCC28711 UCC28712 UCC28713 layoutex3.gif Figure 30. Layout Example Schematic