The capacitance on VDD needs to supply the device operating current until the output of the converter reaches the target minimum operating voltage. At this time the auxiliary winding can sustain the voltage to the UCC28750. The input VDD capacitance is determind by the on current of the controller and the output voltage rise time of the application. The VDD capacitor must be able to keep the VDD pin voltage above 9V, V_uvlo(off), until the output voltage reflected to the auxiliary can take over as the primary bias to the controller.

The soft start feature in UCC28750 does not ramp to full power deliver in the first steps, therefore a conservative 2ms addition is placed into Equation 27 to help size the input capacitors.

A split diode and capacitor network can be used in flyback designs to lower the initial startup time, but still have a path for a bulk capacitance on the device's input put, as shown Section 7.3.1 and reproduced here for ease of use.

Figure 8-3 Split Diode Biasing Scheme for Use With Startup Resistors

The first capacitor, C_VDD1, is determined by the startup resistor value and the desired turn-on time. The startup resistor values are constrained by power loss and fault requirements as mentioned in Section 7.5.4.

For a design with a typical one second start time, and a startup resistor network with an sum resistance of 1.2MΩ after adding in additional margin. The resulting C_VDD1 value is approximatly 6μF. The nearest standard value is 6.8μF.

C_VDD2 is largely determined by the output voltage rise time and the feedback loop estimates. Those parameters can cause an small overshoot during startup, especially at no load applications. When an overshoot occurs the device can stop switching if the feedback loop pulls down on the FB pin voltage enough to push the control law into the off state ("F" region in Figure 7-9).

The output voltage rise time is derived from the assumed power available to charge the capacitor from zero volts to the programmed output voltage. The "2ms" term added in Equation 27 is to account for the fact that the device's soft start does not output full power in the first two milliseconds which, if not added to the equation, which can understate the rise time of the output voltage.

Typically, the crossover frequency is initially placed at one-tenth the switching frequency of the power stage. That estimate can be used to determine the initial value of C_VDD2. Through experiementation and measurement, the actual crossover frequency can be determined. Using the response time estimate equation from Section 8.2.3.4, Equation 24, the overshoot of the output can be determined by modifying Equation 27 for V_out and adding the t_response estimate into the time term. The overshoot value can then be used to determine the amount of time required for that overshoot to decay back to steady state.

Equation 29 is dependent on the output load. When the output load is near zero, the decay time becomes long and therefore C_VDD2 must be large to survive the decay time. Experimentation and testing must be performed to determine if a "dummy load," a resistor put at the output, is required to lower the decay time if the feedback loop causes too large of an overshoot.

The time for the overshoot to reach down to steady state regulation levels uses the fundamental capacitor equation.

Where

• I_off is the UCC28750 off-state current, typically 350μA

With the large range of t_decay from the sum of t_vo,rise and t_response to the worse case of a one second decay time, C_VDD2 can range from 15μF to 70μF.