JAJSCJ6C September   2016  – October 2024 UCC28950-Q1 , UCC28951-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Dissipation Ratings
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Start-Up Protection Logic
      2. 6.3.2  Voltage Reference (VREF)
      3. 6.3.3  Error Amplifier (EA+, EA–, COMP)
      4. 6.3.4  Soft-Start and Enable (SS/EN)
      5. 6.3.5  Light-Load Power Saving Features
      6. 6.3.6  Adaptive Delay, (Delay Between OUTA and OUTB, OUTC and OUTD (DELAB, DELCD, ADEL))
      7. 6.3.7  Adaptive Delay (Delay Between OUTA and OUTF, OUTB and OUTE (DELEF, ADELEF)
      8. 6.3.8  Minimum Pulse (TMIN)
      9. 6.3.9  Burst Mode
      10. 6.3.10 Switching Frequency Setting
      11. 6.3.11 Slope Compensation (RSUM)
      12. 6.3.12 Dynamic SR ON/OFF Control (DCM Mode)
      13. 6.3.13 Current Sensing (CS)
      14. 6.3.14 Cycle-by-Cycle Current Limit Current Protection and Hiccup Mode
      15. 6.3.15 Synchronization (SYNC)
      16. 6.3.16 Outputs (OUTA, OUTB, OUTC, OUTD, OUTE, OUTF)
      17. 6.3.17 Supply Voltage (VDD)
      18. 6.3.18 Ground (GND)
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Power Loss Budget
        2. 7.2.2.2  Preliminary Transformer Calculations (T1)
        3. 7.2.2.3  QA, QB, QC, QD FET Selection
        4. 7.2.2.4  Selecting LS
        5. 7.2.2.5  Selecting Diodes DB and DC
        6. 7.2.2.6  Output Inductor Selection (LOUT)
        7. 7.2.2.7  Output Capacitance (COUT)
        8. 7.2.2.8  Select FETs QE and QF
        9. 7.2.2.9  Input Capacitance (CIN)
        10. 7.2.2.10 Current Sense Network (CT, RCS, R7, DA)
          1. 7.2.2.10.1 Voltage Loop Compensation Recommendation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Community Resources
    5. 8.5 Trademarks
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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発注情報

6.3.14 Cycle-by-Cycle Current Limit Current Protection and Hiccup Mode

The cycle-by-cycle current limit provides peak current limiting on the primary side of the converter when the load current exceeds its predetermined threshold. For peak current mode control, a certain leading edge blanking time is needed to prevent the controller from false tripping due to switching noise. An internal 30ns filter at the CS input is provided. The total propagation delay TCS from CS pin to outputs is 100ns. An external RC filter is still needed if the power stage requires more blanking time. The 2.0V ±3% cycle-by-cycle current limit threshold is optimized for efficient current transformer based sensing. The duration when a converter operates at cycle-by-cycle current limit depends on the value of soft-start capacitor and how severe the overcurrent condition is. This is achieved by the internal discharge current IDS Equation 16 and Equation 17 at SS pin.

Equation 16. I D S ( l e a d e r ) = - 25 × 1 - D + 5   µ A
Equation 17. I D S ( f o l l o w e r ) = - 25 × 1 - D   µ A

The soft-start capacitor value also determines the so-called hiccup mode off-time duration. The behavior of the converter during different modes of operation, along with related soft-start capacitor charge and discharge currents are shown in Figure 6-15.

UCC28950-Q1 UCC28951-Q1 Timing Diagram of Soft-Start Voltage VSS Figure 6-15 Timing Diagram of Soft-Start Voltage VSS

The largest discharge current of 20µA is when the duty cycle is close to zero. This current sets the shortest operation time during the cycle-by-cycle current limit and is defined in Equation 18 and Equation 19

Equation 18. T C L ( o n _ l e a d e r ) = C S S × ( 4.65   V - 3.7   V ) 20   µ A
Equation 19. T C L ( o n _ f o l l o w e r ) = C S S × ( 4.65   V - 3.7   V ) 25   µ A

Thus, if the soft-start capacitor CSS = 100nF is selected, then the TCL(on) time is 5ms.

To calculate the hiccup off time TCL(off) before the restart, use Equation 20 or Equation 21.

Equation 20. TCL(off_leader)=CSS×(3.6V-0.55V)2.5µA
Equation 21. TCL(off_follower)=CSS×(3.6V-0.55V)4.9µA

With the same soft-start capacitor value at 100nF, the off-time before the restart is 122ms. If the overcurrent condition occurs before the soft-start capacitor voltage reaches the 3.7V threshold during start-up, the controller limits the current but the soft-start capacitor continues to be charged. As soon as the 3.7V threshold is reached, the soft-start voltage is quickly pulled up to the 4.65V threshold by an internal 1kΩ RDS(on) switch and the cycle-by-cycle current limit duration timing starts by discharging the soft-start capacitor. Depending on specific design requirements, the user can override this default behavior by applying external charge or discharge currents to the soft-start capacitor. The whole cycle-by-cycle current limit and hiccup operation is shown in Figure 6-15. In this example, the cycle-by-cycle current limit lasts about 5ms followed by 122ms of off-time.

Similarly to the overcurrent condition, the hiccup mode with the restart can be disabled by the user if a pullup resistor of 261kΩ is connected between the SS and VREF pins. The controller remains in the latch-off mode if an overcurrent condition occurs. In this case, calculate an external soft-start capacitor value with the additional pullup current taken into account. The latch-off mode can be reset externally if the soft-start capacitor is forcibly discharged below 0.55V or the VDD voltage is lowered below the UVLO threshold.