JAJSHT1G December   2009  – November 2022 UCC28C40-Q1 , UCC28C41-Q1 , UCC28C42-Q1 , UCC28C43-Q1 , UCC28C44-Q1 , UCC28C45-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Detailed Pin Description
        1. 8.3.1.1 COMP
        2. 8.3.1.2 FB
        3. 8.3.1.3 CS
        4. 8.3.1.4 RT/CT
        5. 8.3.1.5 GND
        6. 8.3.1.6 OUT
        7. 8.3.1.7 VDD
        8. 8.3.1.8 VREF
      2. 8.3.2  Undervoltage Lockout
      3. 8.3.3  ±1% Internal Reference Voltage
      4. 8.3.4  Current Sense and Overcurrent Limit
      5. 8.3.5  Reduced-Discharge Current Variation
      6. 8.3.6  Oscillator Synchronization
      7. 8.3.7  Soft Start
      8. 8.3.8  Enable and Disable
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Voltage Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 UVLO Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  Input Bulk Capacitor and Minimum Bulk Voltage
        3. 9.2.2.3  Transformer Turns Ratio and Maximum Duty CycleG
        4. 9.2.2.4  Transformer Inductance and Peak Currents
        5. 9.2.2.5  Output Capacitor
        6. 9.2.2.6  Current Sensing Network
        7. 9.2.2.7  Gate Drive Resistor
        8. 9.2.2.8  VREF Capacitor
        9. 9.2.2.9  RT/CT
        10. 9.2.2.10 Start-Up Circuit
        11. 9.2.2.11 Voltage Feedback Compensation
          1. 9.2.2.11.1 Power Stage Poles and Zeroes
          2. 9.2.2.11.2 Slope Compensation
          3. 9.2.2.11.3 Open-Loop Gain
          4. 9.2.2.11.4 Compensation Loop
      3. 9.2.3 Application Curves
      4. 9.2.4 Power Supply Recommendations
      5. 9.2.5 Layout
        1. 9.2.5.1 Layout Guidelines
          1. 9.2.5.1.1 Precautions
          2. 9.2.5.1.2 Feedback Traces
          3. 9.2.5.1.3 Bypass Capacitors
          4. 9.2.5.1.4 Compensation Components
          5. 9.2.5.1.5 Traces and Ground Planes
        2. 9.2.5.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Related Links
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.4 Current Sense and Overcurrent Limit

An external series resistor (RCS) senses the current and converts this current into a voltage that becomes the input to the CS pin. The CS pin is the noninverting input to the PWM comparator. The CS input is compared to a signal proportional to the error amplifier output voltage; the gain of the current sense amplifier is typically 3 V/V. The peak ISENSE current is determined using Equation 2

Equation 2. GUID-174478CF-380D-4F38-BC1A-88738CE01C1E-low.gif

The typical value for VCS is 1 V. A small RC filter (RCSF and CCSF) may be required to suppress switch transients caused by the reverse recovery of a secondary side diode or equivalent capacitive loading in addition to parasitic circuit impedances. The time constant of this filter should be considerably less than the switching period of the converter.

GUID-CC48CD9F-D3AF-435D-A3C3-6BA910E323C4-low.gifFigure 8-3 Current-Sense Circuit Schematic

Cycle-by-cycle pulse width modulation performed at the PWM comparator essentially compares the error amplifier output to the current sense input. This is not a direct volt-to-volt comparison, as the error amplifier output network incorporates two diodes in series with a resistive divider network before connecting to the PWM comparator. The two-diode drop adds an offset voltage that enables zero duty cycle to be achieved with a low amplifier output. The 2R/R resistive divider facilitates the use of a wider error amplifier output swing that can be more symmetrically centered on the 2.5-V noninverting input voltage.

The 1-V zener diode associated with the PWM comparator’s input from the error amplifier is not an actual diode in the device’s design, but an indication that the maximum current sense input amplitude is 1 V (typical). When this threshold is reached, regardless of the error amplifier output voltage, cycle-by-cycle current limiting occurs, and the output pulse width is terminated within 35 ns (typical). The minimum value for this current limit threshold is 0.9 V with a 1.1-V maximum. In addition to the tolerance of this parameter, the accuracy of the current sense resistor, or current sense circuitry, must be taken into account. It is advised to factor in the worst case of primary and secondary currents when sizing the ratings and worst-case conditions in all power semiconductors and magnetic components.