JAJSHT1G December   2009  – November 2022 UCC28C40-Q1 , UCC28C41-Q1 , UCC28C42-Q1 , UCC28C43-Q1 , UCC28C44-Q1 , UCC28C45-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Detailed Pin Description
        1. 8.3.1.1 COMP
        2. 8.3.1.2 FB
        3. 8.3.1.3 CS
        4. 8.3.1.4 RT/CT
        5. 8.3.1.5 GND
        6. 8.3.1.6 OUT
        7. 8.3.1.7 VDD
        8. 8.3.1.8 VREF
      2. 8.3.2  Undervoltage Lockout
      3. 8.3.3  ±1% Internal Reference Voltage
      4. 8.3.4  Current Sense and Overcurrent Limit
      5. 8.3.5  Reduced-Discharge Current Variation
      6. 8.3.6  Oscillator Synchronization
      7. 8.3.7  Soft Start
      8. 8.3.8  Enable and Disable
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Voltage Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 UVLO Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  Input Bulk Capacitor and Minimum Bulk Voltage
        3. 9.2.2.3  Transformer Turns Ratio and Maximum Duty CycleG
        4. 9.2.2.4  Transformer Inductance and Peak Currents
        5. 9.2.2.5  Output Capacitor
        6. 9.2.2.6  Current Sensing Network
        7. 9.2.2.7  Gate Drive Resistor
        8. 9.2.2.8  VREF Capacitor
        9. 9.2.2.9  RT/CT
        10. 9.2.2.10 Start-Up Circuit
        11. 9.2.2.11 Voltage Feedback Compensation
          1. 9.2.2.11.1 Power Stage Poles and Zeroes
          2. 9.2.2.11.2 Slope Compensation
          3. 9.2.2.11.3 Open-Loop Gain
          4. 9.2.2.11.4 Compensation Loop
      3. 9.2.3 Application Curves
      4. 9.2.4 Power Supply Recommendations
      5. 9.2.5 Layout
        1. 9.2.5.1 Layout Guidelines
          1. 9.2.5.1.1 Precautions
          2. 9.2.5.1.2 Feedback Traces
          3. 9.2.5.1.3 Bypass Capacitors
          4. 9.2.5.1.4 Compensation Components
          5. 9.2.5.1.5 Traces and Ground Planes
        2. 9.2.5.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Related Links
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
9.2.2.11.2 Slope Compensation

Slope compensation is the large signal subharmonic instability that can occur with duty cycles that may extend beyond 50% where the rising primary side inductor current slope may not match the falling secondary side current slope. The subharmonic oscillation would result in an increase in the output voltage ripple and may even limit the power handling capability of the converter.

The target of slope compensation is to achieve an ideal quality coefficient (QP), equal to 1 at half of the switching frequency. The QP is calculated with Equation 31.

Equation 31. GUID-358E077D-D70D-466B-94AC-4364C73B988D-low.gif

where

  • D is the primary side switch duty cycle
  • MC is the slope compensation factor, which is defined with Equation 32
Equation 32. GUID-413D141A-E17B-452A-85E8-7947D7CED118-low.gif

where

  • Se is the compensation ramp slope
  • Sn is the inductor rising slope

The optimal goal of the slope compensation is to achieve QP = 1; upon rearranging Equation 32 the ideal value of slope compensation factor is determined:

Equation 33. GUID-3766671A-1F9C-44CF-A6F6-6F6E4E7C2983-low.gif

For this design to have adequate slope compensation, MC must be 2.193 when D reaches it maximum value of 0.627.

The inductor rising slope (Sn) at the CS pin is calculated with Equation 34.

Equation 34. GUID-2453C23E-FFFB-4833-91AB-3DD68F436A3D-low.gif

The compensation slope (Se) is calculated with Equation 35.

Equation 35. GUID-58FBD8C8-4B38-4C42-926C-7AC5386EFD30-low.gif

The compensation slope is added into the system through RRAMP and RCSF. The CRAMP is an AC-coupling capacitor that allows the voltage ramp of the oscillator to be used without adding an offset to the current sense; select a value to approximate a high-frequency short circuit, such as 10 nF, as a starting point and make adjustments if required. The RRAMP and RCSF resistors form a voltage divider from the oscillator charge slope and this proportional ramp is injected into the CS pin to add slope compensation. Choose the value of RRAMP to be much larger than the RRT resistor so that it does not load down the internal oscillator and result in a frequency shift. The oscillator charge slope is calculated using the peak-to-peak voltage of the RT/CT sawtooth waveform (VOSCpp) equal to 1.9 V, and the minimum ON time, as shown in Equation 37.

Equation 36. GUID-CD6EFFCE-B6B1-4F3D-975F-0A7E62A95ED1-low.gif
Equation 37. GUID-EA7E6F8A-60BA-4E8A-8817-31332CBDD16D-low.gif

To achieve a 44.74-mV/µs compensation slope, RCSF is calculated with Equation 38. In this design, RRAMP is selected as 24.9 kΩ, a 3.8-kΩ resistor was selected for RCSF.

Equation 38. GUID-FEFB8404-EB20-41A8-8432-F72C1DE1229E-low.gif

It has to be noticed that due to the PN junction of the BJT transistor, it can only source current, which means the capacitor CRAMP can only be charged, not discharged. Therefore, an extra discharge resistor RDIS is needed. Choose RDIS to be 1/10 of the RRAMP.