JAJSHT1G December   2009  – November 2022 UCC28C40-Q1 , UCC28C41-Q1 , UCC28C42-Q1 , UCC28C43-Q1 , UCC28C44-Q1 , UCC28C45-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Detailed Pin Description
        1. 8.3.1.1 COMP
        2. 8.3.1.2 FB
        3. 8.3.1.3 CS
        4. 8.3.1.4 RT/CT
        5. 8.3.1.5 GND
        6. 8.3.1.6 OUT
        7. 8.3.1.7 VDD
        8. 8.3.1.8 VREF
      2. 8.3.2  Undervoltage Lockout
      3. 8.3.3  ±1% Internal Reference Voltage
      4. 8.3.4  Current Sense and Overcurrent Limit
      5. 8.3.5  Reduced-Discharge Current Variation
      6. 8.3.6  Oscillator Synchronization
      7. 8.3.7  Soft Start
      8. 8.3.8  Enable and Disable
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Voltage Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 UVLO Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  Input Bulk Capacitor and Minimum Bulk Voltage
        3. 9.2.2.3  Transformer Turns Ratio and Maximum Duty CycleG
        4. 9.2.2.4  Transformer Inductance and Peak Currents
        5. 9.2.2.5  Output Capacitor
        6. 9.2.2.6  Current Sensing Network
        7. 9.2.2.7  Gate Drive Resistor
        8. 9.2.2.8  VREF Capacitor
        9. 9.2.2.9  RT/CT
        10. 9.2.2.10 Start-Up Circuit
        11. 9.2.2.11 Voltage Feedback Compensation
          1. 9.2.2.11.1 Power Stage Poles and Zeroes
          2. 9.2.2.11.2 Slope Compensation
          3. 9.2.2.11.3 Open-Loop Gain
          4. 9.2.2.11.4 Compensation Loop
      3. 9.2.3 Application Curves
      4. 9.2.4 Power Supply Recommendations
      5. 9.2.5 Layout
        1. 9.2.5.1 Layout Guidelines
          1. 9.2.5.1.1 Precautions
          2. 9.2.5.1.2 Feedback Traces
          3. 9.2.5.1.3 Bypass Capacitors
          4. 9.2.5.1.4 Compensation Components
          5. 9.2.5.1.5 Traces and Ground Planes
        2. 9.2.5.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Related Links
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2.4 Transformer Inductance and Peak Currents

For this design example, the transformer magnetizing inductance is selected based upon the CCM condition. An inductance value that allows the converter to stay in CCM over a wider operating range before transitioning into discontinuous current mode is used to minimize losses due to otherwise high currents and also to decrease the output ripple. The design of the transformer in this example sizes the inductance so the converter enters CCM operation at approximately 10% load and minimum bulk voltage to minimize output ripple.

The inductor (LP) for a CCM flyback can be calculated using Equation 11.

Equation 11. GUID-D8E3AD1A-4D5C-4968-B962-9403A40F41B1-low.gif

where

  • PIN is estimated by dividing the maximum output power (POUT) by the target efficiency (η)
  • fSW is the switching frequency of the converter

For the UCC28C42-Q1 the switching frequency is equal to the oscillator frequency and is set to 110 kHz. Selecting fSW to be 110 kHz provides a good compromise between size of magnetics, switching losses, and places the first harmonic below the 150-kHz lower limit of EN55022. Therefore, the transformer inductance must be approximately 1.8 mH. A 1.5 mH inductance is chosen as the magnetizing inductance, LP, value for this design.

Based on calculated inductor value and the switching frequency, the current stress of the MOSFET and output diode can be calculated.

The peak current in the primary-side MOSFET of a CCM flyback can be calculated as shown in Equation 12.

Equation 12. GUID-9F12DFC1-9497-4518-87FB-F12CFDA21AA0-low.gif

The MOSFET peak current is 1.36 A. The RMS current of the MOSFET is calculated to be 0.97 A as shown in Equation 13. Therefore, IRFB9N65A is selected to be used as the primary-side switch.

Equation 13. GUID-39854C11-D28E-4648-B825-11CFC17787B5-low.gif

The output diode peak current is equal to the MOSFET peak current reflected to the secondary side.

Equation 14. GUID-9BE6A3E8-B0EB-4EBD-999A-3C4DD6C0861F-low.gif

The diode average current is equal to the total output current (4 A) combined with a required 60-V rating and 13.6-A peak current requirement, a 48CTQ060-1 is selected for the output diode.