JAJSNJ5C june   2022  – march 2023 UCC28C50 , UCC28C51 , UCC28C52 , UCC28C53 , UCC28C54 , UCC28C55 , UCC28C56H , UCC28C56L , UCC28C57H , UCC28C57L , UCC28C58 , UCC28C59 , UCC38C50 , UCC38C51 , UCC38C52 , UCC38C53 , UCC38C54 , UCC38C55

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Detailed Pin Description
        1. 8.3.1.1 COMP
        2. 8.3.1.2 FB
        3. 8.3.1.3 CS
        4. 8.3.1.4 RT/CT
        5. 8.3.1.5 GND
        6. 8.3.1.6 OUT
        7. 8.3.1.7 VDD
        8. 8.3.1.8 VREF
      2. 8.3.2  Undervoltage Lockout
      3. 8.3.3  ±1% Internal Reference Voltage
      4. 8.3.4  Current Sense and Overcurrent Limit
      5. 8.3.5  Reduced-Discharge Current Variation
      6. 8.3.6  Oscillator Synchronization
      7. 8.3.7  Soft-Start Timing
      8. 8.3.8  Enable and Disable
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Voltage Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 UVLO Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Input Bulk Capacitor and Minimum Bulk Voltage
        2. 9.2.2.2  Transformer Turns Ratio and Maximum Duty Cycle
        3. 9.2.2.3  Transformer Inductance and Peak Currents
        4. 9.2.2.4  Output Capacitor
        5. 9.2.2.5  Current Sensing Network
        6. 9.2.2.6  Gate Drive Resistor
        7. 9.2.2.7  VREF Capacitor
        8. 9.2.2.8  RT/CT
        9. 9.2.2.9  Start-Up Circuit
        10. 9.2.2.10 Voltage Feedback Compensation
          1. 9.2.2.10.1 Power Stage Poles and Zeroes
          2. 9.2.2.10.2 Slope Compensation
          3. 9.2.2.10.3 Open-Loop Gain
          4. 9.2.2.10.4 Compensation Loop
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Precautions
        2. 9.4.1.2 Feedback Traces
        3. 9.4.1.3 Bypass Capacitors
        4. 9.4.1.4 Compensation Components
        5. 9.4.1.5 Traces and Ground Planes
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

VVDD = 20V for UCC28C56H/L, UCC28C57H/L, and UCC28C58/9, VVDD = 15 V for all other device options, RRT = 10 kΩ, CCT = 3.3 nF, CVDD = 0.1 µF and no load on the outputs, –40°C ≤ TJ ≤ 125°C for the UCC28C5x, 0°C ≤ TJ ≤ 85°C, for the UCC38C5x (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REFERENCE
VVREF VREF voltage, initial accuracy TJ = 25°C, IOUT = 1 mA 4.95 5 5.05 V
Line regulation 12 V ≤ VVDD ≤ 25 V 0.2 20 mV
Load regulation 1 mA to 20 mA 3 25 mV
Temperature stability(2) 0.2 0.4 mV/°C
Total output variation(2) 4.85 5.15 V
VREF noise voltage(2) 10 Hz to 10 kHz, TJ = 25°C 50 µV
Long term stability(2) 1000 hours, TJ = 125°C 5 25 mV
IVREF Output short circuit (source current) 30 45 55 mA
OSCILLATOR
fOSC Initial accuracy(3) TJ = 25°C 50.5 53 55 kHz
Voltage stability 12 V ≤ VVDD ≤ 25 V 0.2% 1%
Temperature stability(2) TJ(MIN) to TJ(MAX) 1% 2.5%
Amplitude RT/CT pin peak-to-peak voltage 1.9 V
Discharge current(4) TJ = 25°C, VRT/CT = 2 V 7.7 8.4 9 mA
VRT/CT = 2 V 7.2 8.4 9.5
ERROR AMPLIFIER
VFB Feedback input voltage, initial accuracy VCOMP = 2.5 V, TJ = 25°C 2.475 2.5 2.525 V
Feedback input voltage, total variation VCOMP = 2.5 V 2.45 2.5 2.55 V
IFB Input bias current (source current) VFB = 5 V 0.1 2 µA
AVOL Open-loop voltage gain 2 V ≤ VOUT ≤ 4 V 65 90 dB
Unity gain bandwidth(2)

1

1.5

 MHz
PSRR Power supply rejection ratio 12 V ≤ VVDD ≤ 25 V 60 dB
Output sink current VFB = 2.7 V, VCOMP = 1.1 V 2 14 mA
Output source current VFB = 2.3 V, VCOMP = 5 V 0.5 1 mA
VOH High-level COMP voltage VFB = 2.7 V, RCOMP = 15 kΩ COMP to GND VREF–0.2 V
VOL Low-level COMP voltage VFB = 2.7 V, RCOMP = 15 kΩ COMP to VREF 0.1 1.1 V
CURRENT SENSE
ACS Gain(5)(1) 2.85 3 3.15 V/V
VCS Maximum input signal VFB < 2.4 V 0.9 1 1.1 V
PSRR Power supply rejection ratio(2)(5) 12 V ≤ VVDD ≤ 25 V 70 dB
ICS Input bias current (source current) 0.1 2 µA
tD CS to output delay 35 70 ns
COMP to CS offset VCS = 0 V 1.15 V
OUTPUT
VOUT(low) RDS(on) pulldown ISINK = 200 mA 5.5 15 Ω
VOUT(high) RDS(on) pullup ISOURCE = 200 mA 10 25 Ω
tRISE Rise time TJ = 25°C, COUT = 1 nF 25 50 ns
tFALL Fall time TJ = 25°C, COUT = 1 nF 20 40 ns
UNDERVOLTAGE LOCKOUT
VDDON Start threshold(6) UCCx8C52, UCCx8C54 13.5 14.5 15.5 V
UCCx8C53, UCCx8C55 7.8 8.4 9
UCCx8C50, UCCx8C51 6.5 7 7.5

UCC28C56H, UCC28C57H

 17.6 18.8 20

UCC28C56L, UCC28C57L

 17.6 18.8 20

UCC28C58, UCC28C59

 14.8 16 17.2
VDDOFF Minimum operating voltage(6) UCCx8C52, UCCx8C54 8 9 10 V
UCCx8C53, UCCx8C55 7 7.6 8.2
UCCx8C50, UCCx8C51 6.1 6.6 7.1

UCC28C56H, UCC28C57H

 15 15.5 16

UCC28C56L, UCC28C57L

 13.95 14.5 15

UCC28C58, UCC28C59

 12 12.5 13
VDDHyst VDDON - VDDOFF UCCx8C52, UCCx8C54

5.4

5.5

V
UCCx8C53, UCCx8C55

0.8

0.9
UCCx8C50, UCCx8C51

0.4

0.5
UCC28C56H, UCC28C57H

2.6

3.3
UCC28C56L, UCC28C57L

3.65

4.3
UCC28C58, UCC28C59

2.8

3.5
PWM
DMAX Maximum duty cycle UCCx8C52, UCCx8C53, UCCx8C50,VFB < 2.4 V 94% 96%

UCC28C56H, UCC28C56L, UCC28C58,VFB < 2.4 V

 94% 96%
UCCx8C54, UCCx8C55, UCCx8C51,VFB < 2.4 V 47% 48%
UCC28C57H, UCC28C57L, UCC28C59,VFB < 2.4 V 47% 48%
DMIN Minimum duty cycle VFB > 2.6 V 0%
CURRENT SUPPLY
ISTART-UP Start-up current VVDD = VDDON – 0.5 V 50 75 µA
IVDD Operating supply current VFB = VCS = 0 V 1.3 2 mA
(1) For UCC28C56H/L, UCC28C57H/L and UCC28C58/9 adjust VVDD to a value above the start threshold before setting it to 20 V. For all other device options, adjust VVDD to a value above the start threshold before setting it to 15.5 V
(2) Specified by design. Not production tested.
(3) Output frequencies of the UCCx8C51, UCCx8C54, and the UCCx8C55, UCC28C57H/L and the UCC28C59 are half the oscillator frequency.
(4) Oscillator discharge current is measured with RRT = 10 kΩ to VREF.
(5) Parameter measured at trip point of latch with VFB = 0 V. Gain is defined as ACS = ΔVCOMP / ΔVCS , 0 V ≤ VCS ≤ 900 mV.
(6) VDDON, VDDOFF and VREF are tracking each other in the same direction. (Minimum VDDOFF is due to minimum VDDON.)