JAJSNJ5C june   2022  – march 2023 UCC28C50 , UCC28C51 , UCC28C52 , UCC28C53 , UCC28C54 , UCC28C55 , UCC28C56H , UCC28C56L , UCC28C57H , UCC28C57L , UCC28C58 , UCC28C59 , UCC38C50 , UCC38C51 , UCC38C52 , UCC38C53 , UCC38C54 , UCC38C55

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Detailed Pin Description
        1. 8.3.1.1 COMP
        2. 8.3.1.2 FB
        3. 8.3.1.3 CS
        4. 8.3.1.4 RT/CT
        5. 8.3.1.5 GND
        6. 8.3.1.6 OUT
        7. 8.3.1.7 VDD
        8. 8.3.1.8 VREF
      2. 8.3.2  Undervoltage Lockout
      3. 8.3.3  ±1% Internal Reference Voltage
      4. 8.3.4  Current Sense and Overcurrent Limit
      5. 8.3.5  Reduced-Discharge Current Variation
      6. 8.3.6  Oscillator Synchronization
      7. 8.3.7  Soft-Start Timing
      8. 8.3.8  Enable and Disable
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Voltage Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 UVLO Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Input Bulk Capacitor and Minimum Bulk Voltage
        2. 9.2.2.2  Transformer Turns Ratio and Maximum Duty Cycle
        3. 9.2.2.3  Transformer Inductance and Peak Currents
        4. 9.2.2.4  Output Capacitor
        5. 9.2.2.5  Current Sensing Network
        6. 9.2.2.6  Gate Drive Resistor
        7. 9.2.2.7  VREF Capacitor
        8. 9.2.2.8  RT/CT
        9. 9.2.2.9  Start-Up Circuit
        10. 9.2.2.10 Voltage Feedback Compensation
          1. 9.2.2.10.1 Power Stage Poles and Zeroes
          2. 9.2.2.10.2 Slope Compensation
          3. 9.2.2.10.3 Open-Loop Gain
          4. 9.2.2.10.4 Compensation Loop
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Precautions
        2. 9.4.1.2 Feedback Traces
        3. 9.4.1.3 Bypass Capacitors
        4. 9.4.1.4 Compensation Components
        5. 9.4.1.5 Traces and Ground Planes
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-A0F28CFE-F7AF-4839-A226-C4597D6FB385-low.svgFigure 6-1 D Package 8-Pin SOIC (Top View)
GUID-4B1EB7C8-C869-4B62-8002-F21D86B41510-low.svgFigure 6-2 DGK Package, 8-Pin VSSOP (Top View)
Table 6-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
COMP1OThis pin provides the output of the error amplifier for compensation. In addition, the COMP pin is frequently used as a control port, by utilizing a secondary-side error amplifier to send an error signal across the secondary-primary isolation boundary through an opto-isolator. The error amplifier is internally current limited so the user can command zero duty cycle by externally forcing COMP to GND.
CS3IPrimary-side current sense pin. The current sense pin is the noninverting input to the PWM comparator. Connect to current sensing resistor. This signal is compared to a signal proportional to the error amplifier output voltage. The PWM uses this to terminate the OUT switch conduction. A voltage ramp can be applied to this pin to run the device with a voltage mode control configuration.
FB2IThis pin is the inverting input to the error amplifier. FB is used to control the power converter voltage-feedback loop for stability. The noninverting input to the error amplifier is internally trimmed to 2.5 V ± 1%.
GND5—Ground return pin for the output driver stage and the logic level controller section.
OUT6OThe output of the on-chip drive stage. OUT is intended to directly drive a MOSFET. The OUT pin in the UCCx8C50, UCCx8C52, UCCx8C53, UCC28C56H/L and UCC28C58 is the same frequency as the oscillator, and can operate near 100% duty cycle. In the UCCx8C51, UCCx8C54, and UCCx8C55, UCC28C57H/L and UCC28C59, the frequency of OUT is one-half that of the oscillator due to an internal T flipflop. This limits the maximum duty cycle to < 50%. Peak currents of up to 1 A are sourced and sunk by this pin. OUT is actively held low when VDD is below the turn-on threshold.
RT/CT4I/OFixed frequency oscillator set point. Connect timing resistor (RRT) to VREF and timing capacitor (CCT) to GND from this pin to set the switching frequency. For best performance, keep the timing capacitor lead to the device GND as short and direct as possible. If possible, use separate ground traces for the timing capacitor and all other functions. The switching frequency (fSW) of the UCCx8C50, UCCx8C52, UCCx8C53, UCC28C56H/L and UCC28C58 gate drive is equal to fOSC; the switching frequency of the UCCx8C51, UCCx8C54, and UCCx8C55, UCC28C57H/L and UCC28C59 is equal to half of the fOSC.
VDD7IAnalog controller bias input that provides power to the device. Total VDD current is the sum of the quiescent VDD current and the average OUT current. A bypass capacitor, typically 0.1 µF, connected directly to GND with minimal trace length, is required on this pin. Additional capacitance at least 10 times greater than the gate capacitance of the main switching FET used in the design and at least 10 times greater than the capacitance on the VREF pin used in the design are also required on VDD.
VREF8O5-V reference voltage. VREF is used to provide charging current to the oscillator timing capacitor through the timing resistor. It is important for reference stability that VREF is bypassed to GND with a ceramic capacitor connected as close to the pin as possible. A minimum value of 0.1 µF ceramic is required. Additional VREF bypassing is required for external loads on VREF. No external voltage higher than specified VREF is allowed to superimposed to VREF pin since VREF is an ouput.
(1) I = input, O = output, G = ground