JAJSHD6B August   2016  – May  2019 UCD90320

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     アプリケーション概略図
  4. 4 改訂履歴
  5. 5 概要(続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Non-Volatile Memory Characteristics
    7. 7.7 I2C/PMBus Interface Timing Requirements
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 TI Fusion Digital Power Designer software
      2. 8.3.2 PMBUS Interface
      3. 8.3.3 Rail Setup
    4. 8.4 Device Functional Modes
      1. 8.4.1  Rail Monitoring Configuration
      2. 8.4.2  GPI Configuration
      3. 8.4.3  Rail Sequence Configuration
      4. 8.4.4  Fault Responses Configuration
      5. 8.4.5  GPO Configuration
        1. 8.4.5.1 Command Controlled GPO
        2. 8.4.5.2 Logic GPO
      6. 8.4.6  Margining Configuration
      7. 8.4.7  Pin Selected Rail States Configuration
      8. 8.4.8  Watchdog Timer
      9. 8.4.9  System Reset Function
      10. 8.4.10 Cascading Multiple Devices
      11. 8.4.11 Rail Monitoring
      12. 8.4.12 Status Monitoring
      13. 8.4.13 Data and Error Logging to EEPROM Memory
      14. 8.4.14 Black Box First Fault Logging
      15. 8.4.15 PMBus Address Selection
      16. 8.4.16 ADC Reference
      17. 8.4.17 Device Reset
      18. 8.4.18 Brownout
      19. 8.4.19 Internal Fault Management
    5. 8.5 Device Configuration and Programming
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 コミュニティ・リソース
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.1 Design Requirements

UCD90320 requires decoupling capacitors on the V33D, V33A, BPCAP, and (if applicable) VREFA+ pins. The capacitance values for V33A, BPCAP and VREFA+ are specified in the Electrical Characteristics table. Consider these capacitor design configurations as options.

  • Three 1-μF X7R ceramic capacitors in parallel with two 0.1-μF X7R ceramic capacitors for BPCAP decoupling
  • Two 1-μF X7R ceramic capacitors in parallel with four 0.1-μF X7R ceramic capacitors and two 0.01-μF X7R ceramic capacitors for V33D decoupling
  • One 1-μF X7R ceramic capacitor in parallel with one 0.1-μF X7R ceramic capacitor and one 0.01-μF X7R ceramic capacitor for V33A decoupling. A 1-Ω resistor can placed between V33D and V33A to decouple the noise on V33D from V33A.
  • One 1-μF X7R ceramic capacitor in parallel with one 0.01-μF X7R ceramic capacitor for VREFA+ decoupling (if used)
  • Place decoupling capacitors as close to the device as possible.
  • If an application does not use the RESET signal, the RESET pin must be tied to V33D, either by direct connection to the nearest V33D pin (Pin F10), or by a R-C circuit as shown in Figure 39. The R-C circuit in Figure 39 can be also used to delay reset at power up. If an application uses the RESET external pin, the trace of the RESET signal must be kept as short as possible. Be sure to place any components connected to the RESET signal as close to the device as possible.
  • TI recommends to maintain at least 200-Ω resistance between a low-impedance analog input and a AMON pin. For example, when monitoring a rail voltage without resistor divider, it is recommended to place a 200-Ω resistor at the AMON pin, as shown in Figure 40.
  • PMBus commands(project file , PMBus write script file) method is not recommended for the production programming since GPIO pins may have unexpected behaviors which can disable rails that provide power to device. Data flash hex file or data flash script file shall be used for production programming since GPIO pins are under controlled state.
  • It is mandatory that the V33D power shall be stable and no device reset shall be fired during the device programming. Data flash may be corrupted if failed to follow these rules.
UCD90320 reset_with-rc_circuit_slusch8.gifFigure 39. RESET Pin With R-C Network
UCD90320 monx_with_analog_inputs_slusch8.gifFigure 40. Example of Analog Inputs