SWRS152N June   2013  – April 2021 WL1801MOD , WL1805MOD , WL1831MOD , WL1835MOD

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Attributes
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  External Digital Slow Clock Requirements
    5. 8.5  Thermal Resistance Characteristics for MOC 100-Pin Package
    6. 8.6  WLAN Performance: 2.4-GHz Receiver Characteristics
    7. 8.7  WLAN Performance: 2.4-GHz Transmitter Power
    8. 8.8  WLAN Performance: Currents
    9. 8.9  Bluetooth Performance: BR, EDR Receiver Characteristics—In-Band Signals
    10. 8.10 Bluetooth Performance: Transmitter, BR
    11. 8.11 Bluetooth Performance: Transmitter, EDR
    12. 8.12 Bluetooth Performance: Modulation, BR
    13. 8.13 Bluetooth Performance: Modulation, EDR
    14. 8.14 Bluetooth low energy Performance: Receiver Characteristics – In-Band Signals
    15. 8.15 Bluetooth low energy Performance: Transmitter Characteristics
    16. 8.16 Bluetooth low energy Performance: Modulation Characteristics
    17. 8.17 Bluetooth BR and EDR Dynamic Currents
    18. 8.18 Bluetooth low energy Currents
    19. 8.19 Timing and Switching Characteristics
      1. 8.19.1 Power Management
        1. 8.19.1.1 Block Diagram – Internal DC-DCs
      2. 8.19.2 Power-Up and Shut-Down States
      3. 8.19.3 Chip Top-level Power-Up Sequence
      4. 8.19.4 WLAN Power-Up Sequence
      5. 8.19.5 Bluetooth-Bluetooth low energy Power-Up Sequence
      6. 8.19.6 WLAN SDIO Transport Layer
        1. 8.19.6.1 SDIO Timing Specifications
        2. 8.19.6.2 SDIO Switching Characteristics – High Rate
      7. 8.19.7 HCI UART Shared-Transport Layers for All Functional Blocks (Except WLAN)
        1. 8.19.7.1 UART 4-Wire Interface – H4
      8. 8.19.8 Bluetooth Codec-PCM (Audio) Timing Specifications
  9. 9 Detailed Description
    1. 9.1 WLAN Features
    2. 9.2 Bluetooth Features
    3. 9.3 Bluetooth Low Energy Features
    4. 9.4 Device Certification
      1. 9.4.1 FCC Certification and Statement
      2. 9.4.2 Innovation, Science, and Economic Development Canada (ISED)
      3. 9.4.3 ETSI/CE
      4. 9.4.4 MIC Certification
    5. 9.5 Module Markings
    6. 9.6 Test Grades
    7. 9.7 End Product Labeling
    8. 9.8 Manual Information to the End User
  10. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
      1. 10.1.1 Typical Application – WL1835MODGB Reference Design
      2. 10.1.2 Design Recommendations
      3. 10.1.3 RF Trace and Antenna Layout Recommendations
      4. 10.1.4 Module Layout Recommendations
      5. 10.1.5 Thermal Board Recommendations
      6. 10.1.6 Baking and SMT Recommendations
        1. 10.1.6.1 Baking Recommendations
        2. 10.1.6.2 SMT Recommendations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Tools and Software
      3. 11.1.3 Device Support Nomenclature
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 TI Module Mechanical Outline
    2. 12.2 Tape and Reel Information
      1. 12.2.1 Tape and Reel Specification
      2. 12.2.2 Packing Specification
        1. 12.2.2.1 Reel Box
        2. 12.2.2.2 Shipping Box
    3. 12.3 Packaging Information
      1. 12.3.1 PACKAGE OPTION ADDENDUM

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • MOC|100
サーマルパッド・メカニカル・データ
発注情報

8.19.2 Power-Up and Shut-Down States

The correct power-up and shut-down sequences must be followed to avoid damage to the device.

While VBAT or VIO or both are deasserted, no signals should be driven to the device. The only exception is the slow clock that is a fail-safe I/O.

While VBAT, VIO, and slow clock are fed to the device, but WL_EN is deasserted (low), the device is in SHUTDOWN state. In SHUTDOWN state all functional blocks, internal DC-DCs, clocks, and LDOs are disabled.

To perform the correct power-up sequence, assert (high) WL_EN. The internal DC-DCs, LDOs, and clock start to ramp and stabilize. Stable slow clock, VIO, and VBAT are prerequisites to the assertion of one of the enable signals.

To perform the correct shut-down sequence, deassert (low) WL_EN while all the supplies to the device (VBAT, VIO, and slow clock) are still stable and available. The supplies to the chip (VBAT and VIO) can be deasserted only after both enable signals are deasserted (low).

Figure 8-2 shows the general power scheme for the module, including the power-down sequence.

GUID-D18CFD47-99A7-4A6A-9918-7E74759029AB-low.gif
NOTE: 1. Either VBAT or VIO can come up first.
2. VBAT and VIO supplies and slow clock (SCLK), must be stable prior to EN being asserted and at all times
when the EN is active.
3. At least 60 µs is required between two successive device enables. The device is assumed to be in
shutdown state during that period, meaning all enables to the device are LOW for that minimum duration.
4. EN must be deasserted at least 10 µs before VBAT or VIO supply can be lowered (order of supply turn off
after EN shutdown is immaterial).
5. EXT_32K - Fail safe I/O
Figure 8-2 Power-Up System