SWRS152 Data sheet

SWRS152N June 2013 – April 2021 WL1801MOD , WL1805MOD , WL1831MOD , WL1835MOD

PRODUCTION DATA

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

MOC|100

サーマルパッド・メカニカル・データ

発注情報

swrs152n_pm

8.19.6.1 SDIO Timing Specifications

Figure 8-6 and Figure 8-7 show the SDIO switching characteristics over recommended operating conditions and with the default rate for input and output.

Figure 8-6 SDIO Default Input Timing

Figure 8-7 SDIO Default Output Timing

Table 8-1 lists the SDIO default timing characteristics.

Table 8-1 SDIO Default Timing Characteristics

⁽¹⁾		MIN	MAX	UNIT
f_clock	Clock frequency, CLK⁽²⁾	0.0	26.0	MHz
DC	Low, high duty cycle⁽²⁾	40.0%	60.0%
t_TLH	Rise time, CLK⁽²⁾		10.0	ns
t_THL	Fall time, CLK⁽²⁾		10.0	ns
t_ISU	Setup time, input valid before CLK ↑⁽²⁾	3.0		ns
t_IH	Hold time, input valid after CLK ↑⁽²⁾	2.0		ns
t_ODLY	Delay time, CLK ↓ to output valid⁽²⁾	7.0	10.0	ns
C_l	Capacitive load on outputs⁽²⁾		15.0	pF

(1) To change the data out clock edge from the falling edge (default) to the rising edge, set the configuration bit.

(2) Parameter values reflect maximum clock frequency.