SWRS152N June   2013  – April 2021 WL1801MOD , WL1805MOD , WL1831MOD , WL1835MOD

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Attributes
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  External Digital Slow Clock Requirements
    5. 8.5  Thermal Resistance Characteristics for MOC 100-Pin Package
    6. 8.6  WLAN Performance: 2.4-GHz Receiver Characteristics
    7. 8.7  WLAN Performance: 2.4-GHz Transmitter Power
    8. 8.8  WLAN Performance: Currents
    9. 8.9  Bluetooth Performance: BR, EDR Receiver Characteristics—In-Band Signals
    10. 8.10 Bluetooth Performance: Transmitter, BR
    11. 8.11 Bluetooth Performance: Transmitter, EDR
    12. 8.12 Bluetooth Performance: Modulation, BR
    13. 8.13 Bluetooth Performance: Modulation, EDR
    14. 8.14 Bluetooth low energy Performance: Receiver Characteristics – In-Band Signals
    15. 8.15 Bluetooth low energy Performance: Transmitter Characteristics
    16. 8.16 Bluetooth low energy Performance: Modulation Characteristics
    17. 8.17 Bluetooth BR and EDR Dynamic Currents
    18. 8.18 Bluetooth low energy Currents
    19. 8.19 Timing and Switching Characteristics
      1. 8.19.1 Power Management
        1. 8.19.1.1 Block Diagram – Internal DC-DCs
      2. 8.19.2 Power-Up and Shut-Down States
      3. 8.19.3 Chip Top-level Power-Up Sequence
      4. 8.19.4 WLAN Power-Up Sequence
      5. 8.19.5 Bluetooth-Bluetooth low energy Power-Up Sequence
      6. 8.19.6 WLAN SDIO Transport Layer
        1. 8.19.6.1 SDIO Timing Specifications
        2. 8.19.6.2 SDIO Switching Characteristics – High Rate
      7. 8.19.7 HCI UART Shared-Transport Layers for All Functional Blocks (Except WLAN)
        1. 8.19.7.1 UART 4-Wire Interface – H4
      8. 8.19.8 Bluetooth Codec-PCM (Audio) Timing Specifications
  9. 9 Detailed Description
    1. 9.1 WLAN Features
    2. 9.2 Bluetooth Features
    3. 9.3 Bluetooth Low Energy Features
    4. 9.4 Device Certification
      1. 9.4.1 FCC Certification and Statement
      2. 9.4.2 Innovation, Science, and Economic Development Canada (ISED)
      3. 9.4.3 ETSI/CE
      4. 9.4.4 MIC Certification
    5. 9.5 Module Markings
    6. 9.6 Test Grades
    7. 9.7 End Product Labeling
    8. 9.8 Manual Information to the End User
  10. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
      1. 10.1.1 Typical Application – WL1835MODGB Reference Design
      2. 10.1.2 Design Recommendations
      3. 10.1.3 RF Trace and Antenna Layout Recommendations
      4. 10.1.4 Module Layout Recommendations
      5. 10.1.5 Thermal Board Recommendations
      6. 10.1.6 Baking and SMT Recommendations
        1. 10.1.6.1 Baking Recommendations
        2. 10.1.6.2 SMT Recommendations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Tools and Software
      3. 11.1.3 Device Support Nomenclature
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 TI Module Mechanical Outline
    2. 12.2 Tape and Reel Information
      1. 12.2.1 Tape and Reel Specification
      2. 12.2.2 Packing Specification
        1. 12.2.2.1 Reel Box
        2. 12.2.2.2 Shipping Box
    3. 12.3 Packaging Information
      1. 12.3.1 PACKAGE OPTION ADDENDUM

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • MOC|100
サーマルパッド・メカニカル・データ
発注情報

7.1 Pin Attributes

Table 7-1 describes the module pins.

Table 7-1 Pin Attributes
PIN NAME PIN NO. TYPE/DIR SHUTDOWN STATE(1) AFTER POWER UP(1) VOLTAGE LEVEL CONNECTIVITY(2) DESCRIPTION(3)
1801 1805 1831 1835
Clocks and Reset Signals
WL_SDIO_CLK 8 I Hi-Z Hi-Z 1.8 V v v v v WLAN SDIO clock. Must be driven by the host.
EXT_32K 36 ANA – v v v v Input sleep clock: 32.768 kHz
WLAN_EN 40 I PD PD 1.8 V v v v v Mode setting: high = enable
BT_EN 41 I PD PD 1.8 V x x v v Mode setting: high = enable
Power-Management Signals
VIO_IN 38 POW PD PD 1.8 V v v v v Connect to 1.8-V external VIO
VBAT_IN 46 POW VBAT v v v v Power supply input, 2.9 to 4.8 V
VBAT_IN 47 POW VBAT v v v v Power supply input, 2.9 to 4.8 V
TI Reserved
GPIO11 2 I/O PD PD 1.8 V v v v v Reserved for future use. NC if not used.
GPIO9 3 I/O PD PD 1.8 V v v v v Reserved for future use. NC if not used.
GPIO10 4 I/O PU PU 1.8 V v v v v Reserved for future use. NC if not used.
GPIO12 5 I/O PU PU 1.8 V v v v v Reserved for future use. NC if not used.
RESERVED1 21 I PD PD 1.8 V x x x x Reserved for future use. NC if not used.
RESERVED2 22 I PD PD 1.8 V x x x x Reserved for future use. NC if not used.
GPIO4 25 I/O PD PD 1.8 V v v v v Reserved for future use. NC if not used.
RESERVED3 62 O PD PD 1.8 V x x x x Reserved for future use. NC if not used.
WLAN Functional Block: Int Signals
WL_SDIO_CMD_1V8 6 I/O Hi-Z Hi-Z 1.8 V v v v v WLAN SDIO command
WL_SDIO_D0_1V8 10 I/O Hi-Z Hi-Z 1.8 V v v v v WLAN SDIO data bit 0
WL_SDIO_D1_1V8 11 I/O Hi-Z Hi-Z 1.8 V v v v v WLAN SDIO data bit 1
WL_SDIO_D2_1V8 12 I/O Hi-Z Hi-Z 1.8 V v v v v WLAN SDIO data bit 2
WL_SDIO_D3_1V8 13 I/O Hi-Z PU 1.8 V v v v v WLAN SDIO data bit 3. Changes state to PU at WL_EN or BT_EN assertion for card detects. Later disabled by software during initialization.
WL_IRQ_1V8 14 O PD 0 1.8 V v v v v WLAN SDIO out-of-band interrupt line. Set to rising edge (active high) by default. (To extract the debug option WL_RS232_TX/RX interface out, pull up the IRQ line at power up before applying enable.)
RF_ANT2 18 ANA – x v x v 2.4-GHz ANT2 TX, RX; 2.4-GHz secondary antenna MRC/MIMO only.
GPIO2 26 I/O PD PD 1.8 V v v v v WL_RS232_RX (when WLAN_IRQ = 1 at power up)
GPIO1 27 I/O PD PD 1.8 V v v v v WL_RS232_TX (when WLAN_IRQ = 1 at power up)
RF_ANT1 32 ANA – v v v v 2.4-GHz WLAN main antenna SISO, Bluetooth
WL_UART_DBG 42 O PU PU 1.8 V v v v v Option: WLAN logger
Bluetooth Functional Block: Int Signals
BT_UART_DBG 43 O PU PU 1.8 V x x v v Option: Bluetooth logger
BT_HCI_RTS_1V8 50 O PU PU 1.8 V x x v v UART RTS to host. NC if not used.
BT_HCI_CTS_1V8 51 I PU PU 1.8 V x x v v UART CTS from host. NC if not used.
BT_HCI_TX_1V8 52 O PU PU 1.8 V x x v v UART TX to host. NC if not used.
BT_HCI_RX_1V8 53 I PU PU 1.8 V x x v v UART RX from host. NC if not used.
BT_AUD_IN 56 I PD PD 1.8 V x x v v Bluetooth PCM/I2S bus. Data in. NC if not used.
BT_AUD_OUT 57 O PD PD 1.8 V x x v v Bluetooth PCM/I2S bus. Data out. NC if not used.
BT_AUD_FSYNC 58 I/O PD PD 1.8 V x x v v Bluetooth PCM/I2S bus. Frame sync. NC if not used.
BT_AUD_CLK 60 I/O PD PD 1.8 V x x v v Bluetooth PCM/I2S bus. NC if not used.
Ground Pins
GND 1 GND – v v v v
GND 7 GND – v v v v
GND 9 GND – v v v v
GND 15 GND – v v v v
GND 16 GND – v v v v
GND 17 GND – v v v v
GND 19 GND – v v v v
GND 20 GND – v v v v
GND 23 GND – v v v v
GND 24 GND – v v v v
GND 28 GND – v v v v
GND 29 GND – v v v v
GND 30 GND – v v v v
GND 31 GND – v v v v
GND 33 GND – v v v v
GND 34 GND – v v v v
GND 35 GND – v v v v
GND 37 GND – v v v v
GND 39 GND – v v v v
GND 44 GND – v v v v
GND 45 GND – v v v v
GND 48 GND – v v v v
GND 49 GND – v v v v
GND 54 GND – v v v v
GND 55 GND – v v v v
GND 59 GND – v v v v
GND 61 GND – v v v v
GND 63 GND – v v v v
GND 64 GND – v v v v
GND G1 – G36 GND – v v v v
(1) PU = pullup; PD = pulldown; Hi-Z = high-impedance
(2) v = connect; x = no connect
(3) Host must provide PU using a 10-kΩ resistor for all non-CLK SDIO signals.