JAJS367B january   2000  – june 2023 XTR115 , XTR116

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Reverse-Voltage Protection
      2. 7.3.2 Overvoltage Surge Protection
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Transistor
      2. 8.1.2 Minimum Scale Current
      3. 8.1.3 Offsetting the Input
      4. 8.1.4 Maximum Output Current
      5. 8.1.5 Radio Frequency Interference
      6. 8.1.6 Circuit Stability
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-20220329-SS0I-9WR0-KZ32-DSPPV6LHGKG3-low.svg Figure 5-1 D Package, SOIC-8 (Top View)
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NO. NAME
1 VREF Output Reference voltage output (2.5 V for XTR115, 4.096 V for XTR116)
2 IIN Input Current input pin
3 IRET Input Local ground return pin for VREG and VREF
4 IO Output Regulated 4-mA to 20-mA current-loop output
5 E (Emitter) Input Emitter connection for external transistor
6 B (Base) Output Base connection for external transistor
7 V+ Power Loop power supply
8 VREG Output 5-V regulator voltage output