JAJSB16C May 2010 – May 2016 DS92LV2421 , DS92LV2422
PRODUCTION DATA.
DS92LV242xチップセットは、パラレルの24ビットLVCMOSデータ・インターフェイスを、クロック情報が埋め込まれた単一の高速CMLシリアル・インターフェイスへ変換します。この単一のシリアル・ストリームにより、クロックおよびデータ間のスキューの問題が解消され、コネクタのサイズが小さくなり、24ビット以下のバスをFR-4プリント基板のバックプレーンおよび平衡ケーブルで伝送する相互接続のコストを削減できます。さらに、DS92LV242xチップセットには低速の信号用に3ビットの制御バスも搭載されています。これによって、ピクセルごとに24ビット(RGB)までのビデオおよびディスプレイ・アプリケーションに使用できます。
プログラム可能な転送ディエンファシス、受信のイコライゼーション、オンチップでのスクランブル処理、およびDC平衡化により、損失の多いケーブルやバックプレーンでも長距離の転送が可能になります。DS92LV2422は外部のリファレンス・クロックや特別な同期パターンを必要とせず、受信データへ自動的にロックするため、簡単なプラグ・アンド・ゴー操作が可能です。低電圧の差動信号、レシーバのドライブ強度の制御、およびスペクトラム拡散クロック機能を使用することで、EMIが最小限に抑えられます。
DS92LV242xチップセットは、I2Cインターフェイスまたはピン経由でプログラム可能です。At-Speed BIST機能が組み込まれており、リンクの整合性を検証し、システム診断に使用できます。DS92LV2421は48ピンWQFN、DS92LV2422は60ピンWQFNパッケージで提供されます。どちらのデバイスも、産業用温度範囲である–40°C~85°Cの全域で動作します。
型番 | パッケージ | 本体サイズ(公称) |
---|---|---|
DS92LV2421 | WQFN (48) | 7.00mm×7.00mm |
DS92LV2422 | WQFN (60) | 9.00mm×9.00mm |
Changes from B Revision (April 2013) to C Revision
Changes from A Revision (April 2013) to B Revision
PIN | TYPE(1) | DESCRIPTION(2) | |
---|---|---|---|
NAME | NO. | ||
LVCMOS PARALLEL INTERFACE | |||
DI[7:0] | 34, 33, 32, 29, 28, 27, 26, 25 | I | Parallel interface data input pins, LVCMOS with pulldown. For 8-bit RED display: DI7 = R7 – MSB, DI0 = R0 – LSB. |
DI[15:8] | 42, 41, 40, 39, 38, 37, 36, 35 | I | Parallel interface data input pins, LVCMOS with pulldown. For 8-bit GREEN display: DI15 = G7 – MSB, DI8 = G0 – LSB. |
DI[23:16] | 2, 1, 48, 47, 46, 45, 44, 43 | I | Parallel interface data input pins, LVCMOS with pulldown. For 8-bit BLUE display: DI23 = B7 – MSB, DI16 = B0 – LSB. |
CI1 | 5 | I | Control signal input, LVCMOS with pulldown. For display or video application: CI1 = Data enable input. Control signal pulse width must be 3 clocks or longer to be transmitted when the Control signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition pulse when the control signal filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2 transitions per 130 clocks regardless of the control signal filter setting. |
CI2 | 3 | I | Control signal input, LVCMOS with pulldown. For display or video application: CI2 = Horizontal sync input. Control signal pulse width must be 3 clocks or longer to be transmitted when the control signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition pulse when the control signal filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2 transitions per 130 clocks regardless of the control signal filter setting. |
CI3 | 4 | I | Control signal input, LVCMOS with pulldown. For display or video application: CI3 = Vertical sync input. CI3 is limited to 1 transition per 130 clock cycles. Thus, the minimum pulse width allowed is 130 clock cycles wide. |
CLKIN | 10 | I | Clock input, LVCMOS with pulldown. Latch or data strobe edge set by RFB pin. |
CONTROL AND CONFIGURATION | |||
PDB | 21 | I | Power-down mode input, LVCMOS with pulldown. PDB = 1, serializer is enabled (normal operation). Refer to Power-Up Requirements and PDB Pin. PDB = 0, serializer is powered down. When the serializer is in the power-down state, the driver outputs (DOUT±) are both logic high, the PLL is shutdown, IDD is minimized. Control Registers are RESET. |
VODSEL | 24 | I | Differential driver output voltage select (this can also be control by I2C register access), LVCMOS with pulldown. VODSEL = 1, LVDS VOD is ±420 mV, 840 mVp-p (typical) — long cable or de-emphasis apps. VODSEL = 0, LVDS VOD is ±280 mV, 560 mVp-p (typical) — short cable (no de-emphasis), low power mode. |
De-Emph | 23 | I | De-emphasis control (this can also be controlled by I2C register access), analog with pullup. De-emphasis = open (float) - disabled. To enable de-emphasis, tie a resistor from this pin to GND or control through register (see Table 3). |
RFB | 11 | I | Clock input latch or data strobe edge select (this can also be controlled by I2C register access), LVCMOS with pulldown. RFB = 1, parallel interface data and control signals are latched on the rising clock edge. RFB = 0, parallel interface data and control signals are latched on the falling clock edge. |
CONFIG[1:0] | 13, 12 | I | LVCMOS with pulldown. 00: Control Signal Filter DISABLED. 01: Control Signal Filter ENABLED. 10: Reverse compatibility mode to interface with the DS90UR124 or DS99R124Q-Q1. 11: Reverse compatibility mode to interface with the DS90C124. |
ID[X] | 6 | I | I2C serial control bus device ID address select (optional), analog. Resistor to Ground and 10-kΩ pullup to 1.8-V rail (see Table 11). |
SCL | 8 | I | I2C serial control bus clock input (optional), LVCMOS. SCL requires an external pullup resistor to VDDIO. |
SDA | 9 | I/O | I2C serial control bus data input or output (optional), LVCMOS (open drain). SDA requires an external pullup resistor VDDIO. |
BISTEN | 31 | I | BIST mode (optional), LVCMOS with pulldown. BISTEN = 0, BIST is disabled (normal operation). BISTEN = 1, BIST is enabled. |
RES[2:0] | 18, 16, 15 | I | Reserved (tie low), LVCMOS with pulldown. |
CHANNEL-LINK II – CML SERIAL INTERFACE | |||
DOUT+ | 20 | O | Noninverting output, CML. The output must be AC-coupled with a 0.1-µF capacitor. |
DOUT– | 19 | O | Inverting output, CML. The output must be AC-coupled with a 0.1-µF capacitor. |
POWER AND GROUND(3) | |||
VDDL | 7 | P | Logic power, 1.8 V ± 5% |
VDDP | 14 | P | PLL power, 1.8 V ± 5% |
VDDHS | 17 | P | TX high-speed logic power, 1.8 V ± 5% |
VDDTX | 22 | P | Output driver power, 1.8 V ± 5% |
VDDIO | 30 | P | LVCMOS I/O power, 1.8 V ± 5% or 3.3 V ± 10% |
GND | DAP | G | DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connect to the ground plane (GND) with at least 9 vias. |
PIN | TYPE(1) | DESCRIPTION(2) | |
---|---|---|---|
NAME | NO. | ||
LVCMOS PARALLEL INTERFACE | |||
DO[7:0] | 33, 34, 35, 36, 37, 39, 40, 41 | I/O | Parallel interface data output pins, STRAP and LVCMOS. For 8-bit RED display: DO7 = R7 – MSB, DO0 = R0 – LSB. In power down (PDB = 0), outputs are controlled by the OSS_SEL (see Table 7). These pins are inputs during power-up (see Deserializer Strap Input Pins). |
DO[15:8] | 20, 21, 22, 23, 25, 26, 27, 28 | I/O | Parallel interface data output pins, STRAP and LVCMOS. For 8-bit GREEN display: DO15 = G7 – MSB, DO8 = G0 – LSB. In power down (PDB = 0), outputs are controlled by the OSS_SEL (see Table 7). These pins are inputs during power-up (see Deserializer Strap Input Pins). |
DO[23:16] | 9, 10, 11, 12, 14, 17, 18, 19 | I/O | Parallel interface data input pins, STRAP and LVCMOS. For 8-bit BLUE display: DO23 = B7 – MSB, DO16 = B0 – LSB. In power down (PDB = 0), outputs are controlled by the OSS_SEL (see Table 7). These pins are inputs during power-up (see Deserializer Strap Input Pins). |
CO1 | 6 | O | Control signal output, LVCMOS. For display or video application: CO1 = Data enable output. Control signal pulse width must be 3 clocks or longer to be transmitted when the control signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition pulse when the control signal filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2 transitions per 130 clocks regardless of the control signal filter setting. In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 7). |
CO2 | 8 | O | Control signal output, LVCMOS. For display or video application: CO2 = Horizontal sync output. Control signal pulse width must be 3 clocks or longer to be transmitted when the control signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition pulse when the control signal filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2 transitions per 130 clocks regardless of the control signal filter setting. In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 7). |
CO3 | 7 | O | Control signal output, LVCMOS. For display or video application: CO3 = Vertical sync output. CO3 is different than CO1 and CO2 because it is limited to 1 transition per 130 clock cycles. Thus, the minimum pulse width allowed is 130 clock cycles wide. The CONFIG[1:0] pins have no effect on the CO3 signal. In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 7). |
CLKOUT | 5 | O | Pixel clock output, LVCMOS. In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 7). Data strobe edge set by RFB. |
LOCK | 32 | O | LOCK status output, LVCMOS. LOCK = 1, PLL is locked, outputs are active LOCK = 0, PLL is unlocked, DO[23:0], CO1, CO2, CO3 and CLKOUT output states are controlled by OSS_SEL (see Table 7). May be used as link status or to flag when video data is active (ON/OFF). |
PASS | 42 | O | PASS output (BIST mode), LVCMOS. PASS = 1, error free transmission. PASS = 0, one or more errors were detected in the received payload. Route to test point for monitoring, or leave open if unused. |
CONTROL AND CONFIGURATION – STRAP PINS(3) | |||
CONFIG[1:0] | 10 [DO22], 9 [DO23] |
I | STRAP or LVCMOS with pulldown. 00: Control Signal Filter DISABLED. 01: Control Signal Filter ENABLED. 10: Reverse compatibility mode to interface with the DS90UR241 or DS99R241-Q1. 11: Reverse compatibility mode to interface with the DS90C241. |
LF_MODE | 12 [DO20] | I | SSCG low frequency mode, STRAP or LVCMOS with pulldown. Only required when SSCG is enabled, otherwise LF_MODE condition is a DON’T CARE (X). LF_MODE = 1, SSCG in low frequency mode (CLK = 10 to 20 MHz). LF_MODE = 0, SSCG in high frequency mode (CLK = 20 to 65 MHz). This can also be controlled by I2C register access. |
OS_CLKOUT | 11 [DO21] | I | Output CLKOUT slew select, STRAP or LVCMOS with pulldown. OS_CLKOUT = 1, increased CLKOUT slew rate. OS_CLKOUT = 0, normal CLKOUT slew rate (default). This can also be controlled by I2C register access. |
OS_DATA | 14 [DO19] | I | Output DO[23:0], CO1, CO2, CO3 slew select; STRAP or LVCMOS with pulldown. OS_DATA = 1, Increased DO slew rate. OS_DATA = 0, Normal DO slew rate (default). This can also be controlled by I2C register access. |
OP_LOW | 42 [PASS] | I | Outputs held low when LOCK = 1, STRAP or LVCMOS with pulldown. NOTE: Do not use any other strap options with this strap function enabled. OP_LOW = 1, all outputs are held low during power up until released by programming OP_LOW release/set register HIGH. NOTE: Before the device is powered up, the outputs are in TRI-STATE (see Figure 30 and Figure 31). OP_LOW = 0, all outputs toggle normally as soon as LOCK goes high (default). This can also be controlled by I2C register access. |
OSS_SEL | 17 [DO18] | I | Output sleep state select, STRAP or LVCMOS with pulldown. OSS_SEL is used in conjunction with PDB to determine the state of the outputs in power down (see Table 7). NOTE: OSS_SEL strap cannot be used if OP_LOW = 1. This can also be controlled by I2C register access. |
RFB | 18 [DO17] | I | Clock output strobe edge select, STRAP or LVCMOS with pulldown. RFB = 1, parallel interface data and control signals are strobed on the rising clock edge. RFB = 0, parallel interface data and control signals are strobed on the falling clock edge. This can also be controlled by I2C register access. |
EQ[3:0] | 20 [DO15], 21 [DO14], 22 [DO13], 23 [DO12] |
I | Receiver input equalization, STRAP or LVCMOS with pulldown (see Table 4). This can also be controlled by I2C register access. |
OSC_SEL[2:0] | 26 [DO10], 27 [DO9], 28 [DO8] |
I | Oscillator select, STRAP or LVCMOS with pulldown (see Table 8 and Table 9). This can also be controlled by I2C register access. |
SSC[3:0] | 34 [DO6], 35 [DO5], 36 [DO4], 37 [DO3] |
I | Spread spectrum clock generation (SSCG) range select, STRAP or LVCMOS with pulldown (see Table 5 and Table 6). This can also be controlled by I2C register access. |
MAP_SEL[1:0] | 40 [D], 41 [D] |
I | Bit mapping reverse compatibility or DS90UR241 options, STRAP or LVCMOS with pulldown. Pin or register control. Default setting is 00'b (see Table 10). |
CONTROL AND CONFIGURATION | |||
PDB | 59 | I | Power-down mode input, LVCMOS with pulldown. PDB = 1, deserializer is enabled (normal operation). Refer to Power-Up Requirements and PDB Pin. PDB = 0, deserializer is in power down. When the deserializer is in the power-down state, the LVCMOS output state is determined by Table 7. Control registers are RESET. |
ID[X] | 56 | I | I2C serial control bus device ID Address Select (optional), analog. Resistor to ground and 10-kΩ pullup to 1.8-V rail (see Table 11). |
SCL | 3 | I | I2C serial control bus clock input (optional), LVCMOS. SCL requires an external pullup resistor to VDDIO. |
SDA | 2 | I/O | I2C serial control bus data input or output (optional), LVCMOS open drain. SDA requires an external pullup resistor to VDDIO. |
BISTEN | 44 | I | BIST enable input (optional), LVCMOS with pulldown. BISTEN = 0, BIST is disabled (normal operation). BISTEN = 1, BIST is enabled. |
RES | 47 | I | Reserved (tie low), LVCMOS with pulldown. |
NC | 1, 15, 16, 30, 31, 45, 46, 60 | — | Not connected, leave pin open (float). |
CHANNEL-LINK II — CML SERIAL INTERFACE | |||
RIN+ | 49 | I | True input, CML. The input must be AC-coupled with a 0.1-μF capacitor. |
RIN- | 50 | I | Inverting input, CML. The input must be AC-coupled with a 0.1-μF capacitor. |
CMF | 51 | I | Common-mode filter, analog. VCM center-tap is a virtual ground which may be AC-coupled to ground to increase receiver common mode noise immunity. Recommended value is 4.7 μF or higher. |
ROUT+ | 52 | O | True output (receive signal after the equalizer), CML. NC if not used or connect to test point for monitor. Requires I2C control to enable. |
ROUT- | 53 | O | Inverting output (receive signal after the equalizer), CML. NC if not used or connect to test point for monitor. Requires I2C control to enable. |
POWER AND GROUND(4) | |||
VDDL | 29 | P | Logic power, 1.8 V ± 5% |
VDDIR | 48 | P | Input power, 1.8 V ± 5% |
VDDR | 43, 55 | P | RX high-speed logic power, 1.8 V ± 5% |
VDDSC | 4, 58 | P | SSCG power, 1.8 V ± 5% |
VDDPR | 57 | P | PLL power, 1.8 V ± 5% |
VDDCMLO | 54 | P | RX high-speed logic power, 1.8 V ± 5% |
VDDIO | 13, 24, 38 | P | LVCMOS I/O power, 1.8 V ± 5% or 3.3 V ± 10% (VDDIO) |
GND | DAP | G | DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connected to the ground plane (GND) with at least 9 vias. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage, VDDn (1.8 V) | –0.3 | 2.5 | V | |
Supply voltage, VDDIO | –0.3 | 4 | V | |
LVCMOS I/O voltage | –0.3 | VDDIO + 0.3 | V | |
Receiver input voltage | –0.3 | VDD + 0.3 | V | |
Driver output voltage | –0.3 | VDD + 0.3 | V | |
48L RHS package | Maximum power dissipation capacity at 25°C | 225 | mW | |
Derate above 25°C | 1 / RθJA | mW/°C | ||
60L NKB package | Maximum power dissipation capacity at 25°C | 525 | mW | |
Derate above 25°C | 1 / RθJA | mW/°C | ||
Junction temperature, TJ | 150 | °C | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±8000 | V | |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | ||||
Machine model (MM) | ±250 | ||||
IEC 61000-4-2 contact discharge | DOUT+, DOUT- | ≥±8000 | |||
RIN+, RIN- | ≥±8000 | ||||
IEC 61000-4-2 air-gap discharge | DOUT+, DOUT- | ≥±25000 | |||
RIN+, RIN- | ≥±25000 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VDDn | Supply voltage | 1.71 | 1.8 | 1.89 | V |
VDDIO | LVCMOS supply voltage | 1.71 | 1.8 | 1.89 | V |
VDDIO | LVCMOS supply voltage | 3 | 3.3 | 3.6 | V |
Clock frequency | 10 | 75 | MHz | ||
Supply noise(1) | 50 | mVp-p | |||
TA | Operating free-air temperature | –40 | 25 | 85 | °C |
THERMAL METRIC(1) | DS92LV2421 | DS92LV2422 | UNIT | |
---|---|---|---|---|
RHS (WQFN) | NKB (WQFN) | |||
48 PINS | 60 PINS | |||
RθJA | Junction-to-ambient thermal resistance(2) | 30.3 | 26.9 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance(2) | 11.5 | 9.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 7.3 | 6 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.1 | 0.1 | °C/W |
ψJB | Junction-to-board characterization parameter | 7.3 | 6 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 2.7 | 1.5 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
LVCMOS INPUT DC SPECIFICATIONS | ||||||||
VIH | High level input voltage | VDDIO = 3 V to 3.6 V (DI[23:0], CI1,CI2,CI3, CLKIN, PDB, VODSEL, RFB, BISTEN, and CONFIG[1:0] pins) | 2.2 | VDDIO | V | |||
VDDIO = 1.71 V to 1.89 V (DI[23:0], CI1,CI2,CI3, CLKIN, PDB, VODSEL, RFB, BISTEN, and CONFIG[1:0] pins) | 0.65 × VDDIO | VDDIO | ||||||
VIL | Low level input voltage | VDDIO = 3 V to 3.6 V (DI[23:0], CI1,CI2,CI3, CLKIN, PDB, VODSEL, RFB, BISTEN, and CONFIG[1:0] pins) | GND | 0.8 | V | |||
VDDIO = 1.71 V to 1.89 V (DI[23:0], CI1,CI2,CI3, CLKIN, PDB, VODSEL, RFB, BISTEN, and CONFIG[1:0] pins) | GND | 0.35 × VDDIO | ||||||
IIN | Input current | VIN = 0 V or VDDIO (DI[23:0], CI1,CI2,CI3, CLKIN, PDB, VODSEL, RFB, BISTEN, and CONFIG[1:0] pins) | VDDIO = 3 V to 3.6 V | –15 | ±1 | 15 | μA | |
VDDIO = 1.7 V to 1.89 V | –15 | ±1 | 15 | |||||
CML DRIVER DC SPECIFICATIONS | ||||||||
VOD | Differential output voltage | RL = 100 Ω, de-emphasis = disabled (see Figure 2; DOUT+ and DOUT– pins) | VODSEL = 0 | ±205 | ±280 | ±355 | mV | |
VODSEL = 1 | ±320 | ±420 | ±520 | |||||
VODp-p | Differential output voltage (DOUT+) – (DOUT-) |
RL = 100 Ω, de-emphasis = disabled (see Figure 2; DOUT+ and DOUT– pins) | VODSEL = 0 | 560 | mVp-p | |||
VODSEL = 1 | 840 | |||||||
ΔVOD | Output voltage unbalance | RL = 100 Ω, de-emphasis = disabled, VODSEL = L (DOUT+ and DOUT– pins) | 1 | 50 | mV | |||
VOS | Offset voltage (single-ended) |
At TP A and B (see Figure 1), RL = 100 Ω, de-emphasis = disabled (DOUT+ and DOUT– pins) | VODSEL = 0 | 1.65 | V | |||
VODSEL = 1 | 1.575 | |||||||
ΔVOS | Offset voltage unbalance (single-ended) |
At TP A and B (see Figure 1), RL = 100 Ω, de-emphasis = disabled (DOUT+ and DOUT– pins) |
1 | mV | ||||
IOS | Output short circuit current | DOUT± = 0 V, de-emphasis = disabled, VODSEL = 0 (DOUT+ and DOUT– pins) |
–36 | mA | ||||
RTO | Internal output termination resistor | DOUT+ and DOUT– pins | 80 | 100 | 120 | Ω | ||
SUPPLY CURRENT | ||||||||
IDDT1 | Serializer supply current (includes load current) |
RL = 100 Ω, CLKIN = 75 MHz, checker board pattern, de-emphasis = 3 kΩ, VODSEL = H (see Figure 9) |
VDD = 1.89 V | 75 | 90 | mA | ||
VDDIO = 1.89 V | 3 | 5 | ||||||
IDDIOT1 | VDDIO = 3.6 V | 11 | 15 | |||||
IDDT2 | Serializer supply current (includes load current) |
RL = 100 Ω, CLKIN = 75 MHz, checker board pattern, de-emphasis = 6 kΩ, VODSEL = L (see Figure 9) |
VDD = 1.89 V | 65 | 80 | mA | ||
VDDIO = 1.89 V | 3 | 5 | ||||||
IDDIOT2 | VDDIO = 3.6 V | 11 | 15 | |||||
IDDZ | Serializer supply current power-down | PDB = 0 V, All other LVCMOS Inputs = 0 V | VDD = 1.89 V | 40 | 1000 | µA | ||
VDDIO = 1.89 V | 5 | 10 | ||||||
IDDIOZ | VDDIO = 3.6 V | 10 | 20 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
3.3-V I/O LVCMOS DC SPECIFICATIONS (VDDIO = 3 V TO 3.6 V) | |||||||
VIH | High level input voltage | PDB and BISTEN pins | 2.2 | VDDIO | V | ||
VIL | Low level input voltage | PDB and BISTEN pins | GND | 0.8 | V | ||
IIN | Input current | VIN = 0 V or VDDIO (PDB and BISTEN pins) | −15 | ±1 | 15 | μA | |
VOH | High level output voltage | IOH = −2 mA, OS_CLKOUT/DATA = L (DO[23:0], CO1, CO2, CO3, CLKOUT, LOCK, and PASS pins) | 2.4 | VDDIO | V | ||
VOL | Low level output voltage | IOL = 3 mA, OS_CLKOUT/DATA = L (DO[23:0], CO1, CO2, CO3, CLKOUT, LOCK, and PASS pins) | GND | 0.4 | V | ||
IOS | Output short circuit current | VDDIO = 3.3 V, VOUT = 0 V, OS_CLKOUT/DATA = L/H (CLKOUT pin) | 36 | mA | |||
Output short circuit current | VDDIO = 3.3 V, VOUT = 0 V, OS_CLKOUT/DATA = L/H (output pins) | 37 | |||||
IOZ | TRI-STATE output current | PDB = 0 V, OSS_SEL = 0 V, VOUT = H (output pins) | −15 | 15 | µA | ||
1.8-V I/O LVCMOS DC SPECIFICATIONS (VDDIO = 1.71 V to 1.89 V) | |||||||
VIH | High level input voltage | PDB and BISTEN pins | 1.235 | VDDIO | V | ||
VIL | Low level input voltage | PDB and BISTEN pins | GND | 0.595 | V | ||
IIN | Input current | VIN = 0 V or VDDIO (PDB and BISTEN pins) | −15 | ±1 | 15 | μA | |
VOH | High level output voltage | IOH = –2 mA, OS_CLKOUT/DATA = L/H (DO[23:0], CO1, CO2, CO3, CLKOUT, LOCK, and PASS pins) | VDDIO – 0.45 | VDDIO | V | ||
VOL | Low level output voltage | IOL = 2 mA, OS_CLKOUT/DATA = L/H (DO[23:0], CO1, CO2, CO3, CLKOUT, LOCK, and PASS pins) | GND | 0.45 | V | ||
IOS | Output short circuit current | VDDIO = 1.8 V, VOUT = 0 V, OS_CLKOUT/DATA = L/H (CLKOUT pin) | 18 | mA | |||
Output short circuit current | VDDIO = 1.8 V, VOUT = 0 V, OS_CLKOUT/DATA = L/H (output pins) | 18 | |||||
IOZ | TRI-STATE output current | PDB = 0 V, OSS_SEL = 0 V, VOUT = 0 V or VDDIO (output pins) | –15 | 15 | µA | ||
CML RECEIVER DC SPECIFICATIONS | |||||||
VTH | Differential input threshold high voltage | VCM = 1.2 V, RIN+ and RIN- pins (Internal VBIAS) | 50 | mV | |||
VTL | Differential input threshold low voltage | VCM = 1.2 V, RIN+ and RIN- pins (Internal VBIAS) | –50 | mV | |||
VCM | Common mode voltage | RIN+ and RIN- pins (Internal VBIAS) | 1.2 | V | |||
IIN | Input current | VIN = 0 V or VDDIO, RIN+ and RIN- pins | –15 | 15 | µA | ||
RTI | Internal input termination resistor | RIN+ and RIN- pins | 80 | 100 | 120 | Ω | |
LOOP THROUGH CML DRIVER OUTPUT DC SPECIFICATIONS (EQ TEST PORT(1)) | |||||||
VOD | Differential output voltage | ROUT+ and ROUT- pins, RL = 100 Ω | 542 | mV | |||
VOS | Offset voltage (single-ended) |
ROUT+ and ROUT- pins, RL = 100 Ω | 1.4 | V | |||
RT | Internal termination resistor | ROUT+ and ROUT- pins | 80 | 100 | 120 | Ω | |
SUPPLY CURRENT | |||||||
IDD1 | Deserializer supply current (includes load current) | CLKOUT = 75 MHz, checker board pattern, OS_CLKOUT/DATA = H, CL = 4 pF (see Figure 9) |
VDD = 1.89 V | 97 | 115 | mA | |
IDDIO1 | VDDIO = 1.89 V | 40 | 50 | ||||
VDDIO = 3.6 V | 75 | 85 | |||||
IDDZ | Deserializer supply current power down | PDB = 0 V, All other LVCMOS Inputs = 0 V | VDD = 1.89 V | 100 | 3000 | µA | |
VDDIO = 1.89 V | 6 | 50 | |||||
IDDIOZ | VDDIO = 3.6 V | 12 | 100 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VIH | Input high level | SDA and SCL | 2.2 | VDDIO | V | |
VIL | Input low level voltage | SDA and SCL | GND | 0.8 | V | |
VHY | Input hysteresis | >50 | mV | |||
VOL | Output low level voltage(1) | SDA, IOL = 1.25 mA, VDDIO = 3.3 V | 0 | 0.4 | V | |
Iin | Input current | SDA or SCL, Vin = VDDIO or GND | –15 | 15 | µA | |
Cin | Input capacitance | SDA or SCL | <5 | pF |
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
tTCP | Transmit input CLKIN period | 10 MHz to 75 MHz (see Figure 4) | 13.3 | T | 100 | ns |
tTCIH | Transmit input CLKIN high time | 10 MHz to 75 MHz (see Figure 4) | 0.4 × T | 0.5 × T | 0.6 × T | ns |
tTCIL | Transmit input CLKIN low time | 10 MHz to 75 MHz (see Figure 4) | 0.4 × T | 0.5 × T | 0.6 × T | ns |
tCLKT | CLKIN input transition time | 10 MHz to 75 MHz (see Figure 4) | 0.5 | 2.4 | ns | |
SSCIN | CLKIN input | fmod (spread spectrum at 75 MHz) | 35 | kHz | ||
fdev (spread spectrum at 75 MHz) | ±2% |
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
fSCL | SCL clock frequency | Standard mode | 100 | kHz | ||
Fast mode | 400 | |||||
tLOW | SCL low period | Standard mode | 4.7 | μs | ||
Fast mode | 1.3 | |||||
tHIGH | SCL high period | Standard mode | 4 | μs | ||
Fast mode | 0.6 | |||||
tHD;STA | Hold time for a start or a repeated start condition (see Figure 18) | Standard mode | 4 | μs | ||
Fast mode | 0.6 | |||||
tSU:STA | Set up time for a start or a repeated start condition (see Figure 18) | Standard mode | 4.7 | μs | ||
Fast mode | 0.6 | |||||
tHD;DAT | Data hold time (see Figure 18) |
Standard mode | 0 | 3.45 | μs | |
Fast mode | 0 | 0.9 | ||||
tSU;DAT | Data set up time (see Figure 18) |
Standard mode | 250 | ns | ||
Fast mode | 100 | |||||
tSU;STO | Set up time for STOP condition (see Figure 18) |
Standard mode | 4 | μs | ||
Fast mode | 0.6 | |||||
tBUF | Bus free time (between STOP and START; see Figure 18) | Standard mode | 4.7 | μs | ||
Fast mode | 1.3 | |||||
tr | SCL and SDA rise time (see Figure 18) |
Standard mode | 1000 | ns | ||
Fast mode | 300 | |||||
tf | SCL and SDA fall time (see Figure 18) |
Standard mode | 300 | ns | ||
Fast mode | 300 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tLHT | Serializer output low-to-high transition time (see Figure 3) | RL = 100 Ω, de-emphasis = disabled, VODSEL = 0 | 200 | ps | ||
RL = 100 Ω, de-emphasis = disabled, VODSEL = 1 | 200 | |||||
tHLT | Serializer output high-to-low transition time (see Figure 3) | RL = 100 Ω, de-emphasis = disabled, VODSEL = 0 | 200 | ps | ||
RL = 100 Ω, de-emphasis = disabled, VODSEL = 1 | 200 | |||||
tDIS | Input data, setup time (see Figure 4) |
DI[23:0], CI1, CI2, CI3 to CLKIN | 2 | ns | ||
tDIH | Input data, hold time (see Figure 4) |
CLKIN to DI[23:0], CI1, CI2, CI3 | 2 | ns | ||
tXZD | Serializer output active to OFF delay (see Figure 6)(1) | 8 | 15 | ns | ||
tPLD | Serializer PLL lock time (see Figure 5)(1)(2)(3) |
RL = 100 Ω | 1.4 | 10 | ms | |
tSD | Serializer delay, latency (see Figure 7)(1) |
RL = 100 Ω | 144 × T | 145 × T | ns | |
tDJIT | Serializer output total jitter (see Figure 8) |
RL = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 75 MHz | 0.28 | UI(4) | ||
RL = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 43 MHz | 0.27 | |||||
RL = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 10 MHz | 0.35 | |||||
λSTXBW | Serializer jitter transfer (function –3 dB bandwidth) |
RL = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 75 MHz | 3.3 | MHz | ||
RL = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 43 MHz | 2.3 | |||||
RL = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 10 MHz | 0.8 | |||||
δSTX | Serializer jitter transfer (function peaking) |
RL = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 75 MHz | 0.86 | dB | ||
RL = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 43 MHz | 0.83 | |||||
RL = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 10 MHz | 0.28 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
tRCP | CLK output period | tRCP = tTCP (CLKOUT) | 13.3 | T | 100 | ns | |
tRDC | CLK output duty cycle | CLKOUT | SSCG = OFF, 10 to 75 MHz | 40% | 50% | 60% | |
SSCG = ON, 10 to 20 MHz | 35% | 59% | 65% | ||||
SSCG = ON, 10 to 65 MHz | 40% | 53% | 60% | ||||
tCLH | LVCMOS low-to-high transition time (see Figure 10) | DO[23:0], CO1, CO2, CO3 | VDDIO = 1.8 V, CL = 4 pF, OS_CLKOUT/DATA = L | 2.1 | ns | ||
VDDIO = 3.3 V, CL = 4 pF, OS_CLKOUT/DATA = H | 2 | ||||||
tCHL | LVCMOS high-to-low transition time (see Figure 10) | DO[23:0], CO1, CO2, CO3 | VDDIO = 1.8 V, CL = 4 pF, OS_CLKOUT/DATA = L | 1.6 | ns | ||
VDDIO = 3.3 V, CL = 4 pF, OS_CLKOUT/DATA = H | 1.5 | ||||||
tROS | Data valid before CLKOUT, setup time (see Figure 14) | VDDIO = 1.71 to 1.89 V or 3 to 3.6 V, CL = 4 pF (lumped load), DO[23:0], CO1, CO2, CO3 | 0.23 × T | 0.5 × T | ns | ||
tROH | Data valid after CLKOUT, hold time (see Figure 14) | VDDIO = 1.71 to 1.89 V or 3 to 3.6 V, CL = 4 pF (lumped load), DO[23:0], CO1, CO2, CO3 | 0.33 × T | 0.5 × T | ns | ||
tDDLT | Deserializer lock time (see Figure 13) |
CLKOUT = 10 MHz, SSC[3:0] = OFF(1) | 3 | ms | |||
CLKOUT = 75 MHz, SSC[3:0] = OFF(1) | 4 | ||||||
CLKOUT = 10 MHz, SSC[3:0] = ON(1) | 30 | ||||||
CLKOUT = 65 MHz, SSC[3:0] = ON(1) | 6 | ||||||
tDD | Deserializer delay, latency (see Figure 11) | CLKOUT = 10 to 75 MHz, SSC[3:0] = OFF(2) | 139 × T | 140 × T | ns | ||
tDPJ | Deserializer period jitter | SSC[3:0] = OFF(3)(2) | CLKOUT = 10 MHz | 500 | 1000 | ps | |
CLKOUT = 65 MHz | 550 | 1250 | |||||
CLKOUT = 75 MHz | 435 | 900 | |||||
tDCCJ | Deserializer cycle-to-cycle jitter | SSC[3:0] = OFF(4)(2)(5) | CLKOUT = 10 MHz | 375 | 900 | ps | |
CLKOUT = 65 MHz | 500 | 1150 | |||||
CLKOUT = 75 MHz | 460 | 1000 | |||||
tIJT | Deserializer input jitter tolerance (see Figure 16) | EQ = OFF, SSCG = OFF, CLKOUT = 75 MHz |
jitter freq < 2 MHz | 0.9 | UI(6) | ||
jitter freq > 6 MHz | 0.5 | ||||||
BIST MODE | |||||||
tPASS | BIST PASS valid time (see Figure 17) |
BISTEN = 1 | 1 | 10 | μs | ||
SSCG MODE | |||||||
fDEV | Spread spectrum clocking deviation frequency | CLKOUT = 10 to 65 MHz, SSC[3:0] = ON | ±0.5% | ±2% | |||
fMOD | Spread spectrum clocking modulation frequency | CLKOUT = 10 to 65 MHz, SSC[3:0] = ON | 8 | 100 | kHz |
The DS92LV242x chipset transmits and receives 24 bits of data and 3 control signals over a single serial CML pair operating at 280 Mbps to 2.1 Gbps. The serial stream also contains an embedded clock, video control signals, and the DC-balance information which enhances signal quality and supports AC coupling.
The deserializer can attain lock to a data stream without the use of a separate reference clock source, which greatly simplifies system complexity and overall cost. The deserializer also synchronizes to the serializer regardless of the data pattern, delivering true automatic plug and lock performance. It can lock to the incoming serial stream without the need of special training patterns or sync characters. The deserializer recovers the clock and data by extracting the embedded clock information, validating, and then deserializing the incoming data stream, providing a parallel LVCMOS video bus to the display, ASIC, or FPGA.
The DS92LV242x chipset can operate in 24-bit color depth (with DE, HS, VS encoded within the serial data stream). In 18-bit color applications, the three video control signals may be sent encoded within the serial bit stream (restrictions apply, see Video Control Signal Filter – Serializer and Deserializer) along with six additional general-purpose signals.
The DS92LV242x chipset transmits and receives a pixel of data in the following format: C1 and C0 represent the embedded clock in the serial stream. C1 is always high and C0 is always low. The b[23:0] contains the scrambled LVCMOS data. DCB is the DC-Balanced control bit. DCB is used to minimize the short and long-term DC bias on the signal lines. This bit determines if the data is unmodified or inverted. DCA is used to validate data integrity in the embedded data stream and can also contain encoded control (VS, HS, DE). Both DCA and DCB coding schemes are generated by the serializer and decoded by the deserializer automatically. Figure 23 illustrates the serial stream per clock cycle.
NOTE
Figure 23 only illustrates the bits but does not actually represent the bit location as the bits are scrambled and balanced continuously.
When operating the devices in normal mode, the video control signals (DE, HS, VS) have the following restrictions:
Video control signals are defined as low frequency signals with limited transitions. Glitches of a control signal can cause a visual display error. This feature allows for the chipset to validate and filter out any high frequency noise on the control signals (see Figure 24).
The serializer converts a wide parallel input bus to a single serial output data stream and also acts as a signal generator for the chipset Built In Self Test (BIST) mode. The device can be configured through external pins or through the optional serial control bus. The serializer features enhance signal quality on the link by supporting: a selectable VOD level, a selectable de-emphasis signal conditioning, and Channel Link II data coding that provides randomization, scrambling, and DC balancing of the data. The serializer includes multiple features to reduce EMI associated with display data transmission. This includes the randomization and scrambling of the data and system spread spectrum clock support. The serializer features power-saving features with a sleep mode, auto stop clock feature, and optional LVCMOS (1.8 V) parallel bus compatibility (see also Optional Serial Bus Control and Built-In Self Test (BIST)).
Channel Link II serializers and deserializers feature a three-step encoding process that enables the use of AC-coupled interconnects and also helps to manage EMI. The serializer first passes the parallel data through a scrambler which randomizes the data. The randomized data is then DC-balanced. The DC-balanced and randomized data then goes through a bit-shuffling circuit and is transmitted out on the serial line. This encoding process helps to prevent static data patterns on the serial stream. The resulting frequency content of the serial stream ranges from the parallel clock frequency to the serial Nyquist rate. For example, if the serializer and deserializer chip set is operating at a parallel clock frequency of 75 MHz, the resulting frequency content of serial stream ranges from 75 MHz to 1.05 GHz (75 MHz × 28 bits / 2 = 2.1 GHz / 2 = 1.05 GHz).
The serializer CLKIN is capable of tracking spread spectrum clocking (SSC) from a host source. The CLKIN accepts spread spectrum tracking up to 35-kHz modulation and ±0.5, ±1, or ±2% deviations (center spread). The maximum conditions for the CLKIN input are: a modulation frequency of 35 kHz and amplitude deviations of ±2% (4% total).
The serializer differential output voltage may be increased by setting the VODSEL pin high. When VODSEL is low, the DC VOD is at the standard (default) level. When VODSEL is high, the VOD is increased in level. The increased VOD is useful in extremely high noise environments and also on extra long cable length applications. When using de-emphasis, TI recommends setting VODSEL = H to avoid excessive signal attenuation, especially with the larger de-emphasis settings. This feature may be controlled by the external pin or by register.
INPUT | EFFECT | |
---|---|---|
VODSEL | VOD (mV) | VOD (mVp-p) |
H | ±420 | 840 |
L | ±280 | 560 |
The de-emphasis pin controls the amount of de-emphasis beginning one full bit time after a logic transition that the serializer drives. This is useful to counteract loading effects of long or lossy cables. This pin must be left open for standard switching currents (no de-emphasis) or if controlled by register. De-emphasis is selected by connecting a resistor on this pin to ground, with R value between 0.5 kΩ to 1 MΩ, or by register setting. When using de-emphasis, TI recommends to set VODSEL = H.
RESISTOR VALUE (kΩ) | DE-EMPHASIS SETTING |
---|---|
Open | Disabled |
0.6 | –12 dB |
1 | –9 dB |
2 | –6 dB |
5 | –3 dB |
The serializer has a PDB input pin to enable or power down the device. This pin is controlled by the host and is used to save power, disabling the link when it is not needed. In power-down mode, the high-speed driver outputs are both pulled to VDD and present a 0-V VOD state.
NOTE
In power down, the optional serial bus control registers are RESET.
The serializer enters a low power SLEEP state when the CLKIN is stopped. A STOP condition is detected when the input clock frequency is less than 3 MHz. The clock must be held at a static low or high state. When the CLKIN starts again, the serializer locks to the valid input clock and then transmits the serial data to the deserializer.
NOTE
In STOP CLOCK SLEEP, the optional serial bus control register values are RETAINED.
The serializer parallel bus and serial bus interface can operate with 1.8-V or 3.3-V levels (VDDIO) for host compatibility. The 1.8-V levels offer lower noise (EMI) and also system power savings.
The deserializer has a PDB input pin to enable or power down the device. This pin can be controlled by the system to save power, disabling the deserializer when the display is not needed. An auto-detect mode is also available. In this mode, the PDB pin is tied high and the deserializer enters power down when the serial stream stops. When the serial stream starts up again, the deserializer locks to the input stream and assert the LOCK pin and output valid data. In power-down mode, the data and CLKOUT output states are determined by the OSS_SEL status.
NOTE
In power down, the optional serial bus control registers are RESET.
The deserializer enters a low power SLEEP state when the input serial stream is stopped. A STOP condition is detected when the embedded clock bits are not present. When the serial stream starts again, the deserializer then locks to the incoming signal and recover the data.
NOTE
In STOP STREAM SLEEP, the optional serial bus control registers values are RETAINED.
The RFB pin determines the edge that the data is latched on. If RFB is high, input data is latched on the rising edge of the CLKIN. If RFB is low, input data is latched on the falling edge of the CLKIN. Serializer and deserializer may be set differently. This feature may be controlled by the external pin or by register.
The deserializer converts a single input serial data stream to a wide parallel output bus and also provides a signal check for the chipset Built-In Self Test (BIST) mode. The device can be configured through external pins and strap pins or through the optional serial control bus. The deserializer features enhance signal quality on the link by supporting an equalizer input and Channel Link II data coding that provides randomization, scrambling, and DC balancing of the data. The deserializer includes multiple features to reduce EMI associated with display data transmission. This includes the randomization and scrambling of the data and output spread spectrum clock generation (SSCG) support. The deserializer features power-saving features with a power-down mode and optional LVCMOS (1.8 V) interface compatibility.
The deserializer can enable receiver input equalization of the serial stream to increase the eye opening to the deserializer input.
NOTE
This function cannot be seen at the RxIN± input but can be observed at the serial test port (ROUT±) enabled through the serial bus control registers. The equalization feature may be controlled by the external pin or by register.
INPUTS | EFFECT | |||
---|---|---|---|---|
EQ3 | EQ2 | EQ1 | EQ0 | |
L | L | L | H | ≈1.5 dB |
L | L | H | H | ≈3 dB |
L | H | L | H | ≈4.5 dB |
L | H | H | H | ≈6 dB |
H | L | L | H | ≈7.5 dB |
H | L | H | H | ≈9 dB |
H | H | L | H | ≈10.5 dB |
H | H | H | H | ≈12 dB |
X | X | X | L | OFF(1) |
The parallel bus outputs (DO[23:0], CO[3:1], and CLKOUT) of the deserializer feature a selectable output slew. The DATA (DO[23:0], CO[3:1]) are controlled by strap pin or register bit OS_DATA. The CLKOUT is controlled by strap pin or register bit OS_CLKOUT. When the OS_CLKOUT/DATA = H, the maximum slew rate is selected. When the OS_PCLK/DATA = L, the minimum slew rate is selected. Use the higher slew rate setting when driving longer traces or a heavier capacitive load.
The deserializer provides access to the center tap of the internal termination. A capacitor may be placed on this pin for additional common-mode filtering of the differential pair. This can be useful in high-noise environments for additional noise rejection capability. A 4.7-µF capacitor may be connected from this pin to Ground.
The deserializer provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both clock and data outputs are modulated. This aids to lower system EMI. Output SSCG deviations of ±2% (4% total) at up to 100-kHz modulations are available (see Table 5). This feature may be controlled by external strap pins or by register.
NOTE
The device supports SSCG function with CLKOUT = 10 MHz to 65 MHz. When the CLKOUT = 65 MHz to 75 MHz, it is required to disable the SSCG function (SSC[3:0] = 0000).
SSC[3:0] INPUTS LF_MODE = H (10 - 20 MHz) |
RESULT | ||||
---|---|---|---|---|---|
SSC3 | SSC2 | SSC1 | SSC0 | fdev (%) | fmod (kHz) |
L | L | L | L | Off | Off |
L | L | L | H | ±0.5 | CLK/620 |
L | L | H | L | ±1 | |
L | L | H | H | ±1.5 | |
L | H | L | L | ±2 | |
L | H | L | H | ±0.5 | CLK/370 |
L | H | H | L | ±1 | |
L | H | H | H | ±1.5 | |
H | L | L | L | ±2 | |
H | L | L | H | ±0.5 | CLK/258 |
H | L | H | L | ±1 | |
H | L | H | H | ±1.5 | |
H | H | L | L | ±2 | |
H | H | L | H | ±0.5 | CLK/192 |
H | H | H | L | ±1 | |
H | H | H | H | ±1.5 |
The deserializer parallel bus and serial bus interface can operate with 1.8-V or 3.3-V levels (VDDIO) for target (display) compatibility. The 1.8-V levels offer a lower noise (EMI) and also system power savings.
When PDB is driven high, the CDR PLL begins locking to the serial input and LOCK goes from TRI-STATE to low (depending on the value of the OSS_SEL setting). After the DS92LV2422 completes its lock sequence to the input serial data, the LOCK output is driven high, indicating valid data and clock recovered from the serial input is available on the parallel bus and clock outputs. The CLKOUT output is held at its current state at the change from OSC_CLK (if this is enabled through OSC_SEL) to the recovered clock (or vice versa).
If there is a loss of clock from the input serial stream, LOCK is driven low and the state of the outputs are based on the OSS_SEL setting (strap pin configuration or register).
The deserializer provides an optional clock output when the input clock (serial stream) has been lost. This is based on an internal oscillator. The frequency of the oscillator may be selected. This feature may be controlled by the external pin or by register (see Table 8 and Table 9).
INPUTS | OUTPUTS | |||||
---|---|---|---|---|---|---|
SERIAL INPUT | PDB | OSS_SEL | CLKOUT | DO[23:0], CO1, CO2, CO3 | LOCK | PASS |
X | L | L | Z | Z | Z | Z |
X | L | H | Z | Z | Z | Z |
Static | H | L | L | L | L | L |
Static | H | H | Z | Z(1) | L | L |
Active | H | X | Active | Active | H | H |
INPUTS | OUTPUTS | |||
---|---|---|---|---|
EMBEDDED CLK | CLKOUT | DO[23:0], CO1, CO2, CO3 | LOCK | PASS |
See (1) | OSC Output | L | L | H |
Present | Toggling | Active | H | H |
OSC_SEL[2:0] INPUTS | CLKOUT OSCILLATOR FREQUENCY | ||
---|---|---|---|
OSC_SEL2 | OSC_SEL1 | OSC_SEL0 | |
L | L | L | Off – Feature Disabled – Default |
L | L | H | 50 MHz ± 40% |
L | H | L | 25 MHz ± 40% |
L | H | H | 16.7 MHz ± 40% |
H | L | L | 12.5 MHz ± 40% |
H | L | H | 10 MHz ± 40% |
H | H | L | 8.3 MHz ± 40% |
H | H | H | 6.3 MHz ± 40% |
The OP_LOW feature is used to hold the LVCMOS outputs (except for the LOCK output) at a low state. The user must toggle the OP_LOW set / reset register bit to release the outputs to the normal toggling state.
NOTE
The release of the outputs can only occur when LOCK is high. When the OP_LOW feature is enabled, anytime LOCK = low, the LVCMOS outputs toggle to a low state again. The OP_LOW strap pin feature is assigned to output PASS pin 42.
Restrictions on other straps:
Outputs DO[23:0], CO[3:1], and CLKOUT are in TRI-STATE before PDB toggles high, because the OP_LOW strap value has not been recognized until the DS92LV2422 powers up. Figure 30 shows the user controlled release of OP_LOW and automatic reset of OP_LOW set on the falling edge of LOCK. Figure 31 shows the user controlled release of OP_LOW and manual reset of OP_LOW set.
NOTE
Manual reset of OP_LOW can only occur when LOCK is high.
The RFB pin determines the edge that the data is strobed on. If RFB is high, output data is strobed on the rising edge of CLKOUT. If RFB is low, data is strobed on the falling edge of CLKOUT. This allows for inter-operability with downstream devices. The deserializer output does not need to use the same edge as the serializer input. This feature may be controlled by the external pin or by register.
The deserializer provides an optional control signal (C3, C2, C1) filter that monitors the three control signals and eliminates any pulses or glitches that are 1 or 2 CLKOUT periods wide. Control signals must be 3 parallel clock periods wide (in its high or low state, regardless of which state is active). This is set by the CONFIG[1:0] strap option or by I2C register control.
This feature may be controlled by the external pin or by register.
This feature may be controlled by the external pin or by register.
INPUTS | EFFECT | |
---|---|---|
MAP_SEL1 | MAP_SEL0 | |
L | L | Bit 4, Bit 5 on LSB DEFAULT |
L | H | LSB 0 or 1 |
H | H or L | LSB 0 |
Configuration of the device may be done through configuration input pins and the strap input pins, or through the serial control bus. The strap input pins share select parallel bus output pins. They are used to load in configuration values during the initial power-up sequence of the device. Only a pullup on the pin is required when a high is desired. By default, the pad has an internal pulldown and bias low by itself. The recommended value of the pullup is 10 kΩ to VDDIO; open (NC) for low, because no pulldown is required (internal pulldown). If using the serial control bus, no pullups are required.
An optional At-Speed Built-In Self Test (BIST) feature supports the testing of the high-speed serial link. This is useful in the prototype stage, equipment production, in-system test, and for system diagnostics. In BIST mode, only an input clock is required along with control to the serializer and deserializer BISTEN input pins. The serializer outputs a test pattern (PRBS-7) and drives the link at speed. The deserializer detects the PRBS-7 pattern and monitors it for errors. A PASS output pin toggles to flag any payloads that are received with 1 to 24 errors. Upon completion of the test, the result of the test is held on the PASS output until reset (new BIST test or power down). A high on PASS indicates NO ERRORS were detected. A low on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to the deserializer BISTEN pin. During the BIST duration, the deserializer data outputs toggle with a checkerboard pattern.
Inter-operability is supported between this Channel Link II device and all Channel Link II generations (Gen 1, 2, 3). See Sample BIST Sequence for entering BIST mode and control.
See Figure 32 for the BIST mode flow diagram.
Step 1: Place the DS92LV2421 serializer in BIST Mode by setting serializer BISTEN = H. For the DS92LV2421 serializer or DS99R421-Q1 FPD-Link II serializer, BIST Mode is enabled through the BISTEN pin. For the DS90C241 serializer or DS90UR241 serializer, BIST mode is entered by setting all the input data of the device to a low state. A CLKIN is required for BIST. When the deserializer detects the BIST mode pattern and command (DCA and DCB code), the data and control signal outputs are shut off.
Step 2: Place the DS92LV2422 deserializer in BIST mode by setting BISTEN = H. The deserializer is now in BIST mode and checks the incoming serial payloads for errors. If an error in the payload (1 to 24) is detected, the PASS pin switches low for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to determine the payload error rate.
Step 3: To stop BIST mode, the deserializer BISTEN pin is set low. The deserializer stops checking the data, and the final test result is held on the PASS pin. If the test ran error free, the PASS output is high. If there was one or more errors detected, the PASS output is low. The PASS output state is held until a new BIST is run, the device is RESET, or powered down. The BIST duration is user controlled by the duration of the BISTEN signal.
Step 4: To return the link to normal operation, the serializer BISTEN input is set low. The Link returns to normal operation.
Figure 33 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error-free, and Case 2 shows one with multiple errors. In most cases, it is difficult to generate errors due to the robustness of the link (differential data transmission and so forth), thus they may be introduced by greatly extending the cable length, faulting the interconnect, or reducing signal condition enhancements (de-emphasis, VODSEL, or Rx equalization).
It is possible to calculate the approximate Bit Error Rate (BER). The following is required:
The BER is less than or equal to one over the product of 24 times the CLKOUT rate times the test duration. If we assume a 65-MHz clock, a 10-minute (600 seconds) test, and a PASS, the BER is ≤ 1.07 X 10E-12.
BIST mode runs a check on the data payload bits. The LOCK pin also provides a link status. If the recovery of the C0 and C1 bits does not reconstruct the expected clock signal, the LOCK pin switches low. The combination of the LOCK and At-Speed BIST PASS pin provides a powerful tool for system evaluation and performance monitoring.
The serializer and deserializer may also be configured by the use of a serial control bus that is I2C protocol-compatible. By default, the I2C Reg 0x00 = 0x00, and all configuration is set by control or strap pins. Writing reg 0x00 = 0x01 enables or allows configuration by registers; this overrides the control or strap pins. Multiple devices may share the serial control bus, because multiple addresses are supported (see Figure 34).
The serial bus is comprised of three pins. The SCL is a serial bus clock input. The SDA is the serial bus data input or output signal. Both SCL and SDA signals require an external pullup resistor to VDDIO. For most applications, a 4.7-kΩ pullup resistor to VDDIO may be used. The resistor value may be adjusted for capacitive loading and data rate requirements. The signals are either pulled high or driven low.
The third pin is the ID[X] pin. This pin sets one of four possible device addresses. Two different connections are possible:
See Table 11 for the serializer and Table 12 for the deserializer. Do not tie ID[X] directly to VSS.
RESISTOR RID kΩ(1) (5% TOL) |
ADDRESS 7'b |
ADDRESS 8'b 0 APPENDED (WRITE) |
---|---|---|
0.47 | 7b' 110 1001 (h'69) | 8b' 1101 0010 (h'D2) |
2.7 | 7b' 110 1010 (h'6A) | 8b' 1101 0100 (h'D4) |
8.2 | 7b' 110 1011 (h'6B) | 8b' 1101 0110 (h'D6) |
Open | 7b' 110 1110 (h'6E) | 8b' 1101 1100 (h'DC) |
RESISTOR RID kΩ(1) (5% TOL) |
ADDRESS 7'b |
ADDRESS 8'b 0 APPENDED (WRITE) |
---|---|---|
0.47 | 7b' 111 0001 (h'71) | 8b' 1110 0010 (h'E2) |
2.7 | 7b' 111 0010 (h'72) | 8b' 1110 0100 (h'E4) |
8.2 | 7b' 111 0011 (h'73) | 8b' 1110 0110 (h'E6) |
Open | 7b' 111 0110 (h'76) | 8b' 1110 1100 (h'EC) |
The serial bus protocol is controlled by START, START-repeated, and STOP phases. A START occurs when SCL transitions low while SDA is high. A STOP occurs when SDA transition high while SCL is also high (see Figure 35).
To communicate with a remote device, the host controller (master) sends the slave address and listens for a response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't match the slave address of a device, it Not-acknowledges (NACKs) the master by letting SDA be pulled high. ACKs also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after every data byte is successfully received. When the master is reading data, the master ACKs after every data byte is received to let the slave know it wants to receive another data byte. When the master wants to stop reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus begins with either a start condition or a repeated start condition. All communication on the bus ends with a stop condition. A READ is shown in Figure 36 and a WRITE is shown in Figure 37.
NOTE
During initial power-up, a delay of 10 ms is required before the I2C will respond.
If the serial bus is not required, the three pins may be left open (NC).
The DS92LV242x chipset is compatible with other single serial lane Channel Link II or FPD-Link II devices. Configuration modes are provided for reverse compatibility with the DS90C241 / DS90C124 chipset (FPD-Link II Generation 1) and also the DS90UR241 / DS90UR124 chipset (FPD-Link II Generation 2) by setting the respective mode with the CONFIG[1:0] pins on the serializer or deserializer as shown in Table 13 and Table 14. This selection also determines whether the control signal filter feature is enabled or disabled in the normal mode. This feature may be controlled by pin or by register.
CONFIG1 | CONFIG0 | MODE | COMPATIBLE DESERIALIZER DEVICE |
---|---|---|---|
L | L | Normal Mode, Control Signal Filter disabled | DS92LV2422, DS92LV2412, DS92LV0422, DS92LV0412 |
L | H | Normal Mode, Control Signal Filter enabled | DS92LV2422, DS92LV2412, DS92LV0422, DS92LV0412 |
H | L | Reverse Compatibility Mode (FPD-Link II, GEN2) | DS90UR124, DS99R124Q-Q1 |
H | H | Reverse Compatibility Mode (FPD-Link II, GEN1) | DS90C124 |
CONFIG1 | CONFIG0 | MODE | COMPATIBLE SERIALIZER DEVICE |
---|---|---|---|
L | L | Normal Mode, Control Signal Filter disabled | DS92LV2421, DS92LV2411, DS92LV0421, DS92LV0411 |
L | H | Normal Mode, Control Signal Filter enabled | DS92LV2421, DS92LV2411, DS92LV0421, DS92LV0411 |
H | L | Reverse Compatibility Mode (FPD-Link II, GEN2) | DS90UR241, DS99R421-Q1 |
H | H | Reverse Compatibility Mode (FPD-Link II, GEN1) | DS90C241 |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The DS92LV242x chipset is intended for interface between a host (graphics processor) and a display. It supports a 24-bit color depth (RGB888) and up to 1024 x 768 display formats. In a RGB888 application, 24 color bits (D[23:0]), Pixel Clock (CLKIN), and three control bits (C1, C2, C3) are supported across the serial link with CLKIN rates from 10 to 75 MHz. The chipset may also be used in 18-bit color applications. In this application, three to six general-purpose signals may also be sent from host to display.
The deserializer is expected to be placed close to its target device. The interconnect between the deserializer and the target device is typically in the 1 to 3 inch separation range. The input capacitance of the target device is expected to be in the 5 pF to 10 pF range. Take care of the CLKOUT output trace, as this signal is edge sensitive and strobes the data. It is also assumed that the fanout of the deserializer is one. If additional loads need to be driven, a logic buffer or mux device is recommended.
The serializer and deserializer devices support live pluggable applications. The automatic receiver lock to random data plug and go hot insertion capability allows the DS92LV2422 to attain lock to the active data stream during a live insertion event.
Color Mapped Data Pin names are provided to specify a recommended mapping for 24-bit color applications. Seven [7] is assumed to be the MSB, and Zero [0] is assumed to be the LSB. While this is recommended, it is not required. When connecting to earlier generations of FPD-Link II serializer and deserializer devices, a color mapping review is recommended to ensure the correct connectivity is obtained. Table 17 provides examples for interfacing to 18-bit applications with or without the video control signals embedded. The DS92LV2422 deserializer provides additional flexibility with the MAP_SEL feature as well.
18-BIT RGB | 18-BIT RGB | 24-BIT RGB | 2421 PIN NAME | 2422 PIN NAME | 24-BIT RGB | 18-BIT RGB | 18-BIT RGB |
---|---|---|---|---|---|---|---|
LSB R0 | GP0 | R0 | DI0 | DO0 | R0 | GP0 | LSB R0 |
R1 | GP1 | R1 | DI1 | DO1 | R1 | GP1 | R1 |
R2 | R0 | R2 | DI2 | DO2 | R2 | R0 | R2 |
R3 | R1 | R3 | DI3 | DO3 | R3 | R1 | R3 |
R4 | R2 | R4 | DI4 | DO4 | R4 | R2 | R4 |
MSB R5 | R3 | R5 | DI5 | DO5 | R5 | R3 | MSB R5 |
LSB G0 | R4 | R6 | DI6 | DO6 | R6 | R4 | LSB G0 |
G1 | R5 | R7 | DI7 | DO7 | R7 | R5 | G1 |
G2 | GP2 | G0 | DI8 | DO8 | G0 | GP2 | G2 |
G3 | GP3 | G1 | DI9 | DO9 | G1 | GP3 | G3 |
G4 | G0 | G2 | DI10 | DO10 | G2 | G0 | G4 |
MSB G5 | G1 | G3 | DI11 | DO11 | G3 | G1 | MSB G5 |
LSB B0 | G2 | G4 | DI12 | DO12 | G4 | G2 | LSB0 |
B1 | G3 | G5 | DI13 | DO13 | G5 | G3 | B1 |
B2 | G4 | G6 | DI14 | DO14 | G6 | G4 | B2 |
B3 | G5 | G7 | DI15 | DO15 | G7 | G5 | B3 |
B4 | GP4 | B0 | DI16 | DO16 | B0 | GP4 | B4 |
MSB B5 | GP5 | B1 | DI17 | DO17 | B1 | GP5 | MSB B5 |
HS | B0 | B2 | DI18 | DO18 | B2 | B0 | HS |
VS | B1 | B3 | DI19 | DO19 | B3 | B1 | VS |
DE | B2 | B4 | DI20 | DO20 | B4 | B2 | DE |
GP0 | B3 | B5 | DI21 | DO21 | B5 | B3 | GP0 |
GP1 | B4 | B6 | DI22 | DO22 | B6 | B4 | GP1 |
GP2 | B5 | B7 | DI23 | DO23 | B7 | B5 | GP2 |
GND | HS | HS | CI1 | CO1 | HS | HS | GND |
GND | VS | VS | CI2 | CO2 | VS | VS | GND |
GND | DE | DE | CI3 | CO3 | DE | DE | GND |
Scenario 3(3) | Scenario 2(2) | Scenario 1(1) | 2421 Pin Name | 2422 Pin Name | Scenario 1(1) | Scenario 2(2) | Scenario 3(3) |
Figure 38 shows a typical application of the DS92LV2421 serializer in pin control mode for a 24-bit application. The LVDS outputs require 100-nF AC-coupling capacitors to the line. The line driver includes internal termination. Bypass capacitors are placed near the power supply pins. At a minimum, four 0.1-µF capacitors and a 4.7-µF capacitor must be used for local device bypassing. System GPO (General Purpose Output) signals control the PDB and BISTEN pins. In this application, the RFB pin is tied low to latch data on the falling edge of the CLKIN. The application assumes connection to the companion deserializer (DS92LV2422), and therefore the configuration pins CONFIG[1:0] are also both tied low. In this example, the cable is long, and therefore the VODSEL pin is tied high and a De-Emphasis value is selected by the resistor R1. The interface to the host is with 1.8-V LVCMOS levels, thus the VDDIO pin is connected also to the 1.8-V rail. The optional serial bus control is not used in this example, thus the SCL, SDA, and ID[X] pins are left open. A delay cap is placed on the PDB signal to delay the enabling of the device until power is stable.
For this example, Table 18 lists the design parameters.
PARAMETER | EXAMPLE VALUE | |||
---|---|---|---|---|
VDDIO | 1.8 V to 3.3 V | |||
VDDL, VDDP, VDDHS, VDDTX | 1.8 V | |||
AC-Coupling Capacitor for DOUT± | 100 nF |
The DOUT± outputs require 100-nF AC-coupling capacitors to the line. The power supply filter capacitors are placed near the power supply pins. A smaller capacitance capacitor must be located closer to the power supply pins.
The VODSEL pin is tied to VDDIO for the long cable application. The de-emphasis pin may connect a resistor to ground. Refer to Table 3. The PDB and BISTEN pins are assumed to be controlled by a microprocessor. The PDB must remain in a low state until all power supply voltages reach the final voltage. The RFB pin is tied low to latch data on the falling edge of the PCLK and tied high for the rising clock edge. The CONFIG[1:0] pins are set depending on operating modes and backward compatibility. The SCL, SDA, and ID[X] pins are left open when these serial bus control pins are unused. The RES[2:0] pins and DAP must be tied to ground.
Figure 40 shows a typical application of the DS92LV2422 deserializer in pin or strap control mode for a 24-bit application. The LVDS inputs use 100-nF coupling capacitors to the line, and the receiver provides internal termination. Bypass capacitors are placed near the power supply pins. At a minimum, seven 0.1-µF capacitors and two 4.7-µF capacitors must be used for local device bypassing. System General Purpose Output (GPO) signals control the PDB and the BISTEN pins. In this application, the RFB pin is tied low to strobe the data on the falling edge of the CLKOUT.
Because the device is in pin or strap control mode, four 10-kΩ pullup resistors are used on the parallel output bus to select the desired device features. CONFIG[1:0] is set to 01'b for normal mode with control signal filter enabled, and this is accomplished with the strap pullup on DO23. The receiver input equalizer is also enabled and set to provide 7.5 dB of gain, and this is accomplished with EQ[3:0] set to 1001'b with strap pullups on DO12 and DO15. To reduce parallel bus EMI, the SSCG feature is enabled and set to fmod = CLK/2168 and ±1% with SSC[3:0] set to 0010'b and a strap pullup on DO4. The desired features are set with the use of the four pullup resistors.
The interface to the target display is with 3.3-V LVCMOS levels, thus the VDDIO pin is connected to the 3.3-V rail. The optional serial bus control is not used in this example, thus the SCL, SDA and ID[X] pins are left open. A delay cap is placed on the PDB signal to delay the enabling of the device until power is stable.
For this example, Table 19 lists the design parameters.
PARAMETER | EXAMPLE VALUE | |||
---|---|---|---|---|
VDDIO | 1.8 V to 3.3 V | |||
VDDL, VDDSC, VDDPR, VDDR, VDDIR, VDDCMLO |
1.8 V | |||
AC-Coupling Capacitor for DOUT± | 100 nF |
The RIN± inputs require 100-nF AC-coupling capacitors to the line. The power supply filter capacitors are placed near the power supply pins. A smaller capacitance capacitor must be placed closer to the power supply pins.
The device has 22 control and configuration pins that are called strap pins. These pins include an internal pulldown. For a high state, use a 10-kΩ resistor pullup to VDDIO.
The PDB and BISTEN pins are assumed to be controlled by a microprocessor. The PDB has to be in a low state until all power supply voltages reach the final voltage. The SCL, SDA, and ID[X] pins are left open when these serial bus control pins are unused.
The RES pin and DAP must be tied to ground.
The VDD (VDDn and VDDIO) supply ramp must be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms, then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage. When PDB pin is pulled to VDDIO, TI recommends using a 10-kΩ pullup and a 22-µF capacitor to GND to delay the PDB input signal.
Circuit board layout and stack-up for the LVDS serializer and deserializer devices must be designed to provide low-noise power feed to the device. Good layout practice also separates high frequency or high-level inputs and outputs to minimize unwanted stray noise pickup, feedback, and interference. Power system performance may be greatly improved by using thin dielectrics (2 to 4 mils) for power or ground sandwiches. This arrangement provides plane capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at high frequencies and makes the value and placement of external bypass capacitors less critical. External bypass capacitors must include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range of 0.01 µF to 0.1 µF. Tantalum capacitors may be in the 2.2 µF to 10 µF range. Voltage rating of the tantalum capacitors must be at least 5x the power supply voltage being used.
Surface-mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per supply pin, place the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power entry. This is typically in the 50 µF to 100 µF range and smooths low frequency switching noise. TI recommends connecting power and ground pins directly to the power and ground planes with bypass capacitors connected to the plane, with vias on both ends of the capacitor. Connecting power or ground pins to an external bypass capacitor increases the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20 to 30 MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as PLLs.
Use at least a four-layer board with a power and ground plane. Place LVCMOS signals away from the CML lines to prevent coupling from the LVCMOS lines to the CML lines. Closely-coupled differential lines of 100 Ω are typically recommended for LVDS interconnects. The closely coupled lines help to ensure that coupled noise appears as common mode and thus is rejected by the receivers. The tightly coupled lines also radiate less.
Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste deposition. Inspection of the stencil prior to placement of the LLP (WQFN) package is highly recommended to improve board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown below:
DEVICE | PIN COUNT | MKT DWG | PCB I/O PAD SIZE (mm) | PCB PITCH (mm) | PCB DAP SIZE (mm) | STENCIL I/O APERTURE (mm) | STENCIL DAP APERTURE (mm) | NUMBER OF DAP APERTURE OPENINGS | GAP BETWEEN DAP APERTURE (Dim A mm) |
---|---|---|---|---|---|---|---|---|---|
DS92LV2421 | 48 | SQA48A | 0.25 × 0.6 | 0.5 | 5.1 × 5.1 | 0.25 × 0.7 | 1.1 × 1.1 | 16 | 0.2 |
DS92LV2422 | 60 | SQA60B | 0.25 × 0.8 | 0.5 | 7.2 × 7.2 | 0.25 × 0.9 | 1.16 × 1.16 | 25 | 0.3 |
Information on the WQFN style package is provided in Leadless Leadframe Package (LLP) Application Report (SNOA401).
The serializer and deserializer chipset is intended to be used in a point-to-point configuration through a PCB trace or through twisted pair cable. The serializer and deserializer provide internal terminations for a clean signaling environment. The interconnect for CML must present a differential impedance of 100 Ω. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Shielded or un-shielded cables may be used depending upon the noise environment and application requirements.
See AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008) and AN-905 Transmission Line RAPIDESIGNER Operation and Applications Guide (SNLA035) for full details.
Additional general guidance can be found in the LVDS Owner’s Manual, available in PDF format from the TI web site at: www.ti.com/lvds.
The following PCB layout examples are derived from the layout design of the LV24EVK01 Evaluation Module. These graphics and additional layout description are used to demonstrate both proper routing and proper solder techniques when designing in the serializer and deserializer pair.