JAJSC24H June   2013  – November 2016 TPS65132 , TPS65132S

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5  Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Interface Timing Requirements / Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Lockout (UVLO)
      2. 8.3.2 Active Discharge
      3. 8.3.3 Boost Converter
        1. 8.3.3.1 Boost Converter Operation
        2. 8.3.3.2 Power-Up And Soft-Start (Boost Converter)
        3. 8.3.3.3 Power-Down (Boost Converter)
        4. 8.3.3.4 Isolation (Boost Converter)
        5. 8.3.3.5 Output Voltage (Boost Converter)
        6. 8.3.3.6 Advanced Power-Save Mode For Light-Load Efficiency And PFM
      4. 8.3.4 LDO Regulator
        1. 8.3.4.1 LDO Operation
        2. 8.3.4.2 Power-Up And Soft-Start (LDO)
        3. 8.3.4.3 Power-Down And Discharge (LDO)
        4. 8.3.4.4 Isolation (LDO)
        5. 8.3.4.5 Setting The Output Voltage (LDO)
      5. 8.3.5 Negative Charge Pump
        1. 8.3.5.1 Operation
        2. 8.3.5.2 Power-Up And Soft-Start (CPN)
        3. 8.3.5.3 Power-Down And Discharge (CPN)
        4. 8.3.5.4 Isolation (CPN)
        5. 8.3.5.5 Setting The Output Voltage (CPN)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enabling and Disabling the Device
    5. 8.5 Programming
      1. 8.5.1 I2C Serial Interface Description
      2. 8.5.2 I2C Interface Protocol
    6. 8.6 Register Maps
      1. 8.6.1 Registers
        1. 8.6.1.1 VPOS Register - Address: 0x00
        2. 8.6.1.2 VNEG Register - Address 0x01
        3. 8.6.1.3 DLYx Register - Address 0x02 (Only valid for TPS65132Sx)
        4. 8.6.1.4 APPS - SEQU - SEQD - DISP - DISN Register - Address 0x03
        5. 8.6.1.5 Control Register - Address 0xFF
      2. 8.6.2 Factory Default Register Value
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Low-current Applications (≤ 40 mA)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Sequencing
          2. 9.2.1.2.2 Boost Converter Design Procedure
            1. 9.2.1.2.2.1 Inductor Selection (Boost Converter)
            2. 9.2.1.2.2.2 Input Capacitor Selection (Boost Converter)
            3. 9.2.1.2.2.3 Output Capacitor Selection (Boost Converter)
          3. 9.2.1.2.3 Input Capacitor Selection (LDO)
          4. 9.2.1.2.4 Output Capacitor Selection (LDO)
          5. 9.2.1.2.5 Input Capacitor Selection (CPN)
          6. 9.2.1.2.6 Output Capacitor Selection (CPN)
          7. 9.2.1.2.7 Flying Capacitor Selection (CPN)
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Mid-current Applications (≤ 80 mA)
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Boost Converter Design Procedure
            1. 9.2.2.2.1.1 Inductor Selection (Boost Converter)
            2. 9.2.2.2.1.2 Input Capacitor Selection (Boost Converter)
            3. 9.2.2.2.1.3 Output Capacitor Selection (Boost Converter)
          2. 9.2.2.2.2 Input Capacitor Selection (LDO)
          3. 9.2.2.2.3 Output Capacitor Selection (LDO)
          4. 9.2.2.2.4 Input Capacitor Selection (CPN)
          5. 9.2.2.2.5 Output Capacitor Selection (CPN)
          6. 9.2.2.2.6 Flying Capacitor Selection (CPN)
        3. 9.2.2.3 Application Curves
      3. 9.2.3 High-current Applications (≤ 150 mA)
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1 Sequencing
          2. 9.2.3.2.2 SYNC = HIGH
          3. 9.2.3.2.3 Startup
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報
    1. 13.1 CSPパッケージの概要
      1. 13.1.1 チップ・スケール・パッケージの寸法
      2. 13.1.2 RVCパッケージの概要

7 Specifications

7.1 Absolute Maximum Ratings(1)(2)

over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
MIN MAX
Voltage range CFLY1, EN, ENN, ENP, OUTP, REG, SCL, SDA, SW, SYNC, VIN –0.3 7 V
CFLY2, OUTN –7 0.3 V
Continuous total power dissipation See Thermal Information
Operating junction temperature, TJ –40 150 °C
Operating ambient temperature, TA –40 85 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to ground.

7.2 ESD Ratings

VALUE UNIT
VESD Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM) per JEDEC specification JESD22-C101, all pins(2) ±500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN TYP MAX UNIT
VIN Input voltage range 2.5 5.5 V
L Inductor(1) 2.2 4.7 µH
CIN Input capacitor(1)(2) 4.7 µF
CFLY Flying capacitor(1)(2) 2.2 µF
COUTP, COUTN, CREG Output capacitors(1)(2) 4.7 µF
TA Operating ambient temperature –40 85 °C
TJ Operating junction temperature –40 125 °C
(1) Please see Detailed Description section for further information.
(2) X7R (or better dielectric material) is recommended.

7.4 Thermal Information

THERMAL METRIC(1) TPS65132 TPS65132 UNIT
YFF RVC
(15) BALLS (20) PINS
RθJA Junction-to-ambient thermal resistance 76.5 39.0 °C/W
RθJCtop Junction-to-case (top) thermal resistance 0.2 42.7 °C/W
RθJB Junction-to-board thermal resistance 44 13.6 °C/W
ψJT Junction-to-top characterization parameter 1.6 0.6 °C/W
ψJB Junction-to-board characterization parameter 43.4 13.6 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance N/A 3.8 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

VIN = 3.7 V, EN = ENN = ENP = VIN, VPOS = 5.4 V, VNEG = –5.4 V, TA = –40°C to 85°C; typical values are at TA = 25°C
(unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
VIN Input voltage range 2.5 5.5 V
VUVLO Undervoltage lockout threshold VIN rising 2.3 2.5 V
VIN falling 2.1 2.3
IQ Quiescent current 0.54 mA
Thermal shutdown 140 °C
Thermal shutdown hysteresis 5 °C
LOGIC EN, ENN, ENP, SYNC
VIH High level input voltage VIN = 2.5 V to 5.5 V 1.1 V
VIL Low level input voltage 0.4
REN Pulldown resistors 200 kΩ
LOGIC SCL, SDA
VIH High level input voltage VIN = 2.5 V to 5.5 V 1.1 V
VIL Low level input voltage 0.54
BOOST CONVERTER
ILIM Boost converter valley current limit 0.9 1.2 1.5 A
fSW Boost converter switching frequency 1.35 1.80 2.25 MHz
LDO OUTPUT VPOS
VPOS Positive output voltage range 4.0 6.0 V
VPOS_acc Positive output voltage accuracy –1 % +1 %
IPOS Positive output current capability 200 mA
VDO Dropout voltage VREG = VPOS(NOM) = 5.4V, IOUT = 150 mA 160 mV
Line regulation VIN = 2.5 V to 5.5 V, IOUT = 40 mA 2.7 mV
Load regulation ΔIOUT = 80 mA 3.4 %/A
RD Discharge resistor 70 Ω
NEGATIVE CHARGE PUMP OUTPUT VNEG
VNEG Negative output voltage range –6.0 –4.0 V
VNEG_acc Negative output voltage accuracy –1 % +1 %
INEG Negative output current capability 40mA MODE 40 mA
80mA MODE 80
INEG Negative output current capability TPS65132Sx, SYNC = HIGH 150 mA
fOSC Negative charge pump switching frequency 0.8 1.0 1.2 MHz
Line regulation VIN = 2.5 V to 5.5 V, IOUT = 40 mA 3.3 mV
Load regulation ΔIOUT = 80 mA 6.1 %/A
RD Discharge resistor 20 Ω

7.6 I2C Interface Timing Requirements / Characteristics (1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSCL SCL clock frequency Standard mode 100 kHz
Fast mode 400 kHz
tLOW LOW period of the SCL clock Standard mode 4.7 µs
Fast mode 1.3 µs
tHIGH HIGH period of the SCL clock Standard mode 4.0 µs
Fast mode 600 ns
tBUF Bus free time between a STOP and START condition Standard mode 4.7 µs
Fast mode 1.3 µs
thd;STA Hold time for a repeated START condition Standard mode 4.0 µs
Fast mode 600 ns
tsu;STA Setup time for a repeated START condition Standard mode 4.7 µs
Fast mode 600 ns
tsu;DAT Data setup time Standard mode 250 ns
Fast mode 100 ns
thd;DAT Data hold time Standard mode 0.05 3.45 µs
Fast mode 0.05 0.9 µs
tRCL1 Rise time of SCL signal after a repeated START condition and after an acknowledge bit Standard mode 20 + 0.1CB 1000 ns
Fast mode 20 + 0.1CB 1000 ns
tRCL Rise time of SCL signal Standard mode 20 + 0.1CB 1000 ns
Fast mode 20 + 0.1CB 300 ns
tFCL Fall time of SCL signal Standard mode 20 + 0.1CB 300 ns
Fast mode 20 + 0.1CB 300 ns
tRDA Rise time of SDA signal Standard mode 20 + 0.1CB 1000 ns
Fast mode 20 + 0.1CB 300 ns
tFDA Fall time of SDA signal Standard mode 20 + 0.1CB 300 ns
Fast mode 20 + 0.1CB 300 ns
tsu;STO Setup time for STOP condition Standard mode 4.0 µs
Fast mode 600 ns
CB Capacitive load for SDA and SCL 0.4 nF
(1) Industry standard I2C timing characteristics according to I2C-Bus Specification, Version 2.1, January 2000. Not tested in production.
TPS65132 fs_timing_lvs957.gif Figure 1. Serial Interface Timing For F/S-Mode

7.7 Typical Characteristics

VIN= 3.7 V, VPOS= 5.4 V, VNEG= –5.4 V, unless otherwise noted
TPS65132 C044_SLVSBM1.png Figure 2. Shutdown Current (all versions but Ax)
TPS65132 C034_SLVSBM1.png Figure 4. Main Oscillator Frequency
TPS65132 C040_SLVSBM1.png Figure 3. Quiescent Current
TPS65132 C039_SLVSBM1.png Figure 5. UVLO