JAJSC95F December   2012  – December 2017 TPS7A66-Q1 , TPS7A69-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ハードウェア・イネーブル・オプション
      2.      入力電圧センス・オプション
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Enable (EN)
      2. 7.3.2 Regulated Output (VOUT)
      3. 7.3.3 Power-On Reset (PG)
      4. 7.3.4 Reset Delay Timer (CT)
      5. 7.3.5 Sense Comparator (SI and SO for TPS7A69-Q1)
      6. 7.3.6 Adjustable Output Voltage (FB for TPS7A6601-Q1)
      7. 7.3.7 Undervoltage Shutdown
      8. 7.3.8 Low-Voltage Tracking
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Regulation
      2. 7.4.2 Disabled
      3. 7.4.3 Operation With V(VinUVLO)< VIN < VIN(min)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 TPS7A66-Q1 Typical Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Input Capacitor
          2. 8.2.1.2.2 Output Capacitor
        3. 8.2.1.3 Application Curve
      2. 8.2.2 TPS7A69-Q1 Typical Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Low-Voltage Tracking Threshold
        3. 8.2.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Mounting
      2. 10.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance
    2. 10.2 Layout Examples
    3. 10.3 Power Dissipation and Thermal Considerations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 関連リンク
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

4 改訂履歴

Changes from E Revision (November 2014) to F Revision

  • Changed 最初の 2 つの AEC-Q100 小項目の温度範囲を削除し、「特長」のAEC-Q100 試験ガイダンス項目をGo
  • Changed ドキュメント全体で V(Vin) を VIN に、Vin を VIN に、V(Vout) を VOUT に、Vout を VOUT に、V(CT) を VCT にGo
  • Added 「特長」のデバイス接合部温度範囲項目Go
  • Changed ドキュメント全体で関連デバイスを TPS7A66-Q1 および TPS7A69-Q1 にGo
  • Changed ドキュメント全体で MSOP を HVSSOP にGo
  • Changed CT, EN, FB/DNC, PG, SO, and VOUT descriptions in Pin Functions table Go
  • Changed pin names FB/NU to FB/DNC, Vin to VIN, and Vout to VOUT in Pin Configuration and Functions sectionGo
  • Changed SI parameter name description and added maximum specification to SI and FB, SO, PG rows in Absolute Maximum Ratings tableGo
  • Added parameter names to CT and FB, SO, PG rows in Absolute Maximum Ratings tableGo
  • Added lockout to Undervoltage lockout detection parameter nameGo
  • Added up to to Ilkg test conditions Go
  • Added VOUT to unit of V(TH-POR) and V(Thres)Go
  • Added CT to V(th) parameter nameGo
  • Added header for first section of Switching Characteristics tableGo
  • Added UVLO Thresholds vs Temperature and Enable Thresholds vs Temperature figuresGo
  • Added CT Charging Current (VCT = 0) and CT Charging Threshold figuresGo
  • Changed Device Functional Modes sectionGo

Changes from D Revision (October 2014) to E Revision

  • Corrected voltage unit in Handling Ratings table from V to kV Go

Changes from C Revision (December 2013) to D Revision

  • CDM ESC分類レベルを変更Go
  • Changed FB/NC pin to FB/NU in Pin Functions table Added NC and NU notes to pinout drawings Go
  • Removed ESD and Tstg specifications from the Absolute Maximum Ratings tableGo
  • Added ESD Ratings table Go
  • Numerous changes throughout the Electrical Characteristics table Go
  • Added Switching Characteristics tableGo
  • Moved an oscilloscope trace to the Applications Information section Go
  • Changed de-glitch time in Power-On Reset (PG) section Go
  • Changed reset delay timer default delay to 290 µs from 150 µs Go
  • Changed voltage at which Power-on reset initializes to 91.6% of V(Vout)Go
  • Changed selectable output voltage range and calculation for FB resistor divideerGo

Changes from B Revision (August 2013) to C Revision

  • 「概要」セクションの型番に -Q1 を追加して訂正Go
  • Changed Operating ambient temperature to Operating junction temperatureGo
  • Added PSRR graph to Typical CharacteristicsGo
  • Deleted a paragraph from the Thermal Protection sectionGo

Changes from A Revision (March 2013) to B Revision

  • Added two conditions to Vdropout in the Electrical Characteristics tableGo

Changes from * Revision (December 2012) to A Revision

  • Deleted the ORDERING INFORMATION tableGo
  • Changed From: TA Operating ambient temperature range –40 to 125°C To: TJ Operating ambient temperature range –40 to 150°CGo