The resistor R_AB from the DELAB pin, DELAB to GND, along with the resistor divider R_AHI from CS pin to ADEL pin and R_A from ADEL pin to GND sets the delay T_ABSET between one of outputs OUTA or OUTB going low and the other output going high Figure 6-1. The total resistance of this resistor divider should be in the range between 10kΩ and 20kΩ

This delay gradually increases as a function of the CS signal from T_ABSET1, which is measured at V_CS = 1.8V, to T_ABSET2, which is measured at the V_CS = 0.2V. This approach ensures there will be no shoot-through current during the high-side and low-side MOSFET switching and optimizes the delay for acheiving ZVS condition over a wide load current range. The ratio between the longest and shortest delays is set by the resistor divider R_AHI and R_A. The maximum ratio is achieved by tying the CS and ADEL pins together. If ADEL is connected to GND, then the delay is fixed, defined only by the resistor R_AB from DELAB to GND. The delay T_CDSET1 and T_CDSET2 settings and their behaviour for outputs OUTC and OUTD are very similar to the one described for OUTA and OUTB. The difference is that resistor R_CD connected between DELCD pin and GND sets the delay T_CDSET. The ratio between the longest and shortest delays is set by the resistor divider R_AHI and R_A.

The delay time T_ABSET is defined by the following Equation 3 .

where

• the CS, which is the voltage at pin CS, is in volts
• K_A is a numerical gain factor of CS voltage from 0 to 1

The same equation is used to define the delay time T_CDSET in another leg, except R_AB is replaced by R_CD (see Equation 4).

where

• the CS, which is the voltage at pin CS, is in volts
• K_A is a numerical gain factor of CS voltage from 0 to 1

These equations are empirical and they are approximated from measured data. Thus, there is no unit agreement in the equations. As an example, assume R_AB = 15kΩ, CS = 1V and K_A = 0.5. Then the T_ABSET is approximately 90ns.

In Equation 5, K_A is the same and is defined as Equation 5:

K_A sets how the delay varies with the CS pin voltage as shown in Figure 6-2 and Figure 6-3.

TI recommends starting by setting K_A = 0 and set T_ABSET and T_CDSET relatively large using equations or plots in this data sheet to avoid hard switching or even shoot through current. The delay between outputs A, B and C, D set by resistors R_AB and R_CD accordingly. Program the optimal delays at light load first. Then by changing K_A set the optimal delay for the outputs A, B at maximum current. K_A for outputs C, D is the same as for A, B. Usually outputs C, D always have ZVS if sufficient delay is provided.

R_A and R_AHI define the portion of voltage at pin CS applied to the pin ADEL (see Figure 7-3). K_A defines how significantly the delay time depends on CS voltage. K_A varies from 0, where ADEL pin is shorted to ground (R_A = 0) and the delay does not depend on CS voltage, to 1, where ADEL is tied to CS (R_AHI = 0). Setting K_A, R_AB, and R_CD provides the ability to maintain optimal ZVS conditions of primary switches over load current because the voltage at CS pin includes the load current reflected to the primary side through the current-sensing circuit. The plots in Figure 6-2 and Figure 6-3 show the delay time settings as a function of CS voltage and K_A for two different conditions: R_AB = R_CD = 13kΩ (Figure 6-2) and R_AB = R_CD = 90kΩ (Figure 6-3).