JAJSD52A March   2017  – December 2018 OPT3001-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     ブロック図
    2.     スペクトル応答： OPT3001-Q1および肉眼
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Human Eye Matching
      2. 8.3.2 Automatic Full-Scale Range Setting
      3. 8.3.3 Interrupt Operation, INT Pin, and Interrupt Reporting Mechanisms
      4. 8.3.4 I2C Bus Overview
        1. 8.3.4.1 Serial Bus Address
        2. 8.3.4.2 Serial Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 Automatic Full-Scale Setting Mode
      2. 8.4.2 Interrupt Reporting Mechanism Modes
        1. 8.4.2.1 Latched Window-Style Comparison Mode
        2. 8.4.2.2 Transparent Hysteresis-Style Comparison Mode
        3. 8.4.2.3 End-of-Conversion Mode
        4. 8.4.2.4 End-of-Conversion and Transparent Hysteresis-Style Comparison Mode
    5. 8.5 Programming
      1. 8.5.1 Writing and Reading
        1. 8.5.1.1 High-Speed I2C Mode
        2. 8.5.1.2 General-Call Reset Command
        3. 8.5.1.3 SMBus Alert Response
    6. 8.6 Register Maps
      1. 8.6.1 Internal Registers
        1. 8.6.1.1 Register Descriptions
          1. 8.6.1.1.1 Result Register (offset = 00h)
            1. Table 7. Result Register Field Descriptions
          2. 8.6.1.1.2 Configuration Register (offset = 01h) [reset = C810h]
            1. Table 10. Configuration Register Field Descriptions
          3. 8.6.1.1.3 Low-Limit Register (offset = 02h) [reset = C0000h]
            1. Table 11. Low-Limit Register Field Descriptions
          4. 8.6.1.1.4 High-Limit Register (offset = 03h) [reset = BFFFh]
            1. Table 13. High-Limit Register Field Descriptions
          5. 8.6.1.1.5 Manufacturer ID Register (offset = 7Eh) [reset = 5449h]
            1. Table 14. Manufacturer ID Register Field Descriptions
          6. 8.6.1.1.6 Device ID Register (offset = 7Fh) [reset = 3001h]
            1. Table 15. Device ID Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Electrical Interface
      2. 9.1.2 Optical Interface
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Optomechanical Design
        2. 9.2.2.2 Dark Window Selection and Compensation
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報
    1. 13.1 ハンダ付けと取り扱いについての推奨事項
    2. 13.2 DNP (S-PDSO-N6)メカニカル図面

8.6.1.1.2 Configuration Register (offset = 01h) [reset = C810h]

This register controls the major operational modes of the device. This register has 11 fields, which are documented below. If a measurement conversion is in progress when the configuration register is written, the active measurement conversion immediately aborts. If the new configuration register directs a new conversion, that conversion is subsequently started.

Figure 28. Configuration Register
15 14 13 12 11 10 9 8
RN3 RN2 RN1 RN0 CT M1 M0 OVF
R/W R/W R/W R/W R/W R/W R/W R
7 6 5 4 3 2 1 0
CRF FH FL L POL ME FC1 FC0
R R R R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only

Table 10. Configuration Register Field Descriptions

Bit Field Type Reset Description
15:12 RN[3:0] R/W 1100b Range number field (read or write).
The range number field selects the full-scale lux range of the device. The format of this field is the same as the result register exponent field (E[3:0]); see Table 8. When RN[3:0] is set to 1100b (0Ch), the device operates in automatic full-scale setting mode, as described in the Automatic Full-Scale Setting Mode section. In this mode, the automatically chosen range is reported in the result exponent (register 00h, E[3:0]).
The device powers up as 1100 in automatic full-scale setting mode. Codes 1101b, 1110b, and 1111b (0Dh, 0Eh, and 0Fh) are reserved for future use.
11 CT R/W 1b Conversion time field (read or write).
The conversion time field determines the length of the light to digital conversion process. The choices are 100 ms and 800 ms. A longer integration time allows for a lower noise measurement.
The conversion time also relates to the effective resolution of the data conversion process. The 800-ms conversion time allows for the fully specified lux resolution. The 100-ms conversion time with full-scale ranges above 0101b for E[3:0] in the result and configuration registers also allows for the fully specified lux resolution. The 100-ms conversion time with full-scale ranges below and including 0101b for E[3:0] can reduce the effective result resolution by up to three bits, as a function of the selected full-scale range. Range 0101b reduces by one bit. Ranges 0100b, 0011b, 0010b, and 0001b reduces by two bits. Range 0000b reduces by three bits. The result register format and associated LSB weight does not change as a function of the conversion time.
0 = 100 ms
1 = 800 ms
10:9 M[1:0] R/W 00b Mode of conversion operation field (read or write).
The mode of conversion operation field controls whether the device is operating in continuous conversion, single-shot, or low-power shutdown mode. The default is 00b (shutdown mode), such that upon power-up, the device only consumes operational level power after appropriately programming the device.
When single-shot mode is selected by writing 01b to this field, the field continues to read 01b while the device is actively converting. When the single-shot conversion is complete, the mode of conversion operation field is automatically set to 00b and the device is shut down.
When the device enters shutdown mode, either by completing a single-shot conversion or by a manual write to the configuration register, there is no change to the state of the reporting flags (conversion ready, flag high, flag low) or the INT pin. These signals are retained for subsequent read operations while the device is in shutdown mode.
00 = Shutdown (default)
01 = Single-shot
10, 11 = Continuous conversions
8 OVF R 0b Overflow flag field (read-only).
The overflow flag field indicates when an overflow condition occurs in the data conversion process, typically because the light illuminating the device exceeds the programmed full-scale range of the device. Under this condition OVF is set to 1, otherwise OVF remains at 0. The field is reevaluated on every measurement.
If the full-scale range is manually set (RN[3:0] field < 1100b), the overflow flag field can be set while the result register reports a value less than full-scale. This result occurs if the input light has a temporary high spike level that temporarily overloads the integrating ADC converter circuitry but returns to a level within range before the conversion is complete. Thus, the overflow flag reports a possible error in the conversion process. This behavior is common to integrating-style converters.
If the full-scale range is automatically set (RN[3:0] field = 1100b), the only condition that sets the overflow flag field is if the input light is beyond the full-scale level of the entire device. When there is an overflow condition and the full-scale range is not at maximum, the OPT3001-Q1 device aborts its current conversion, sets the full-scale range to a higher level, and starts a new conversion. The flag is set at the end of the process. This process repeats until there is either no overflow condition or until the full-scale range is set to its maximum range.
7 CRF R 0b Conversion ready field (read-only).
The conversion ready field indicates when a conversion completes. The field is set to 1 at the end of a conversion and is cleared (set to 0) when the configuration register is subsequently read or written with any value except one containing the shutdown mode (mode of operation field, M[1:0] = 00b). Writing a shutdown mode does not affect the state of this field; see the Interrupt Reporting Mechanism Modes section for more details.
6 FH R 0b Flag high field (read-only).
The flag high field (FH) identifies that the result of a conversion is larger than a specified level of interest. FH is set to 1 when the result is larger than the level in the high-limit register (register address 03h) for a consecutive number of measurements defined by the fault count field (FC[1:0]). See the Interrupt Reporting Mechanism Modes section for more details on clearing and other behaviors of this field.
5 FL R 0b Flag low field (read-only).
The flag low field (FL) identifies that the result of a conversion is smaller than a specified level of interest. FL is set to 1 when the result is smaller than the level in the low-limit register (register address 02h) for a consecutive number of measurements defined by the fault count field (FC[1:0]). See the Interrupt Reporting Mechanism Modes section for more details on clearing and other behaviors of this field.
4 L R/W 1b Latch field (read or write).
The latch field controls the functionality of the interrupt reporting mechanisms: the INT pin, the flag high field (FH), and flag low field (FL). This bit selects the reporting style between a latched window-style comparison and a transparent hysteresis-style comparison.
0 = The device functions in transparent hysteresis-style comparison operation, where the three interrupt reporting mechanisms directly reflect the comparison of the result register with the high- and low-limit registers with no user-controlled clearing event. See the Interrupt Operation, INT Pin, and Interrupt Reporting Mechanisms section for further details.
1 = The device functions in latched window-style comparison operation, latching the interrupt reporting mechanisms until a user-controlled clearing event.
3 POL R/W 0b Polarity field (read or write).
The polarity field controls the polarity or active state of the INT pin.
0 = The INT pin reports active low, pulling the pin low upon an interrupt event.
1 = Operation of the INT pin is inverted, where the INT pin reports active high, becoming high impedance and allowing the INT pin to be pulled high upon an interrupt event.
2 ME R/W 0b Mask exponent field (read or write).
The mask exponent field forces the result register exponent field (register 00h, bits E[3:0]) to 0000b when the full-scale range is manually set, which can simplify the processing of the result register when the full-scale range is manually programmed. This behavior occurs when the mask exponent field is set to 1 and the range number field (RN[3:0]) is set to less than 1100b. Note that the masking is only performed to the result register. When using the interrupt reporting mechanisms, the result comparison with the low-limit and high-limit registers is unaffected by the ME field.
1:0 FC[1:0] R/W 00b Fault count field (read or write).
The fault count field instructs the device as to how many consecutive fault events are required to trigger the interrupt reporting mechanisms: the INT pin, the flag high field (FH), and flag low field (FL). The fault events are described in the latch field (L), flag high field (FH), and flag low field (FL) descriptions.
00 = One fault count (default)
01 = Two fault counts
10 = Four fault counts
11 = Eight fault counts