JAJSEM0D February   2018  – April 2024 TUSB1044

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Requirements
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 USB 3.1
      2. 6.3.2 DisplayPort
      3. 6.3.3 4-Level Inputs
      4. 6.3.4 Receiver Linear Equalization
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Configuration in GPIO mode
      2. 6.4.2 Device Configuration in I2C Mode
      3. 6.4.3 DisplayPort Mode
      4. 6.4.4 Custom Alternate Mode
      5. 6.4.5 Linear EQ Configuration
      6. 6.4.6 Adjustable VOD Linear Range and DC Gain
      7. 6.4.7 USB3.1 Modes
    5. 6.5 Programming
      1. 6.5.1 Use The Following Procedure to Write to TUSB1044 I2C Registers:
      2. 6.5.2 Use The Following Procedure to Read the TUSB1044 I2C Registers:
      3. 6.5.3 Use The Following Procedure for Setting a Starting Sub-Address for I2C Reads:
    6. 6.6 Register Maps
      1. 6.6.1 TUSB1044 Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 System Examples
      1. 7.3.1 USB 3.1 only (USB/DP Alternate Mode)
      2. 7.3.2 USB3.1 and 2 lanes of DisplayPort
      3. 7.3.3 DisplayPort Only
      4. 7.3.4 USB 3.1 only (USB/Custom Alternate Mode)
      5. 7.3.5 USB3.1 and 1 Lane of Custom Alt Mode
      6. 7.3.6 USB3.1 and 2 Lane of Custom Alt Mode
      7. 7.3.7 USB3.1 and 4 Lane of Custom Alt Mode
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

GUID-F9DE662E-05D4-4A07-BB4A-360EBFE4AA01-low.svgFigure 4-1 RNQ Package40-Pin (WQFN)Top View
Pin Functions
PIN I/O DESCRIPTION
NO. NAME
1 VCC P 3.3 V Power Supply
2 UEQ1/A1 4 Level I This pin along with UEQ0 sets the high-frequency equalizer gain for upstream facing URX1, URX2, UTX1, UTX2 receivers. In I2C Mode, this pin will also set TUSB1044 I2C address. Refer to Table 6-9.
3 CFG0 4 Level I CFG0. This pin along with CFG1 will select VOD linearity range and DC gain for all the downstream and upstream channels. Refer to Table 6-8 for VOD linearity range and DC gain options.
4 CFG1 4 Level I CFG1. This pin along with CFG0 will set VOD linearity range and DC gain for all the downstream and upstream channels. Refer to Table 6-8 for VOD linearity range and DC gain options.
5 SWAP 2 Level I
(PD)		 This pin swaps all the channel directions and EQ settings of downstream facing and upstream facing data path inputs.
0 – Do not swap channel directions and EQ settings (Default)
1. – Swap channel directions and EQ settings.
6 VCC P 3.3V Power Supply
7 SLP_S0# 2 Level I
(PD)		 This pin when asserted low will disable Receiver Detect functionality. While this pin is low and TUSB1044 is in U2/U3, TUSB1044 will disable LOS and LFPS detection circuitry and RX termination for both channels will remain enabled. If this pin is low and TTUSB1044 is in Disconnect state, the RX detect functionality will be disabled and RX termination for both channels will be disabled.
0 – RX Detect disabled
1 – RX Detect enabled (Default)
8 DIR0 2 Level I
(PD)		 This pin along with DIR1 sets the data path signal direction format. Refer to Table 6-4 for signal direction formats.
0 - Source Side (DFP) Alt Mode format
1 - Sink Side (UFP) Alt Mode format
9 URX2p Diff I/O Differential positive input/output for upstream facing RX2 port.
10 URX2n Diff I/O Differential negative input/output for upstream facing RX2 port.
11 DIR1 2 Level I/O
(PD)		 This pin along with DIR0 sets the data path signal direction format. Refer to Table 6-4 for signal direction formats.
0 - DisplayPort Alt Mode format
1 - Custom Alt Mode format
12 UTX2p Diff I/O Differential positive input/output for upstream facing TX2 port.
13 UTX2n Diff I/O Differential negative input/output for upstream facing TX2 port.
14 VIO_SEL 4 Level I/O This pin selects I/O voltage levels for the 2-level GPIO configuration pins and the I2C interface:
0 = 3.3-V configuration I/O voltage, 3.3-V I2C interface (Default)
R = 3.3-V configuration I/O voltage, 1.8-V I2C interface
F = 1.8-V configuration I/O voltage, 3.3-V I2C interface
1 = 1.8-V configuration I/O voltage, 1.8-V I2C interface.
15 UTX1n Diff I/O Differential negative input/output for upstream facing TX1 port.
16 UTX1p Diff I/O Differential positive input/output for upstream facing TX1 port.
17 I2C_EN 4 Level I I2C Programming or Pin Strap Programming Select.
0 = GPIO Mode, AUX Snoop Enabled (I2C disabled)
R = TI Test Mode (I2C enabled)
F = GPIO Mode, AUX Snoop Disabled (I2C disabled)
1 = I2C enabled.
18 URX1n Diff I/O Differential negative input/output for upstream facing RX1 port.
19 URX1p Diff I/O Differential positive input/output for upstream facing RX1 port.
20 VCC P 3.3V Power Supply
21 FLIP/SCL 2 Level I
(PD)
(Failsafe)		 In GPIO mode, this is Flip control pin, otherwise this pin is I2C clock.
22 CTL0/SDA 2 Level I
(PD)
(Failsafe)		 In GPIO mode, this is a USB3.1 Switch control pin, otherwise this pin is I2C data.
23 CTL1 2 Level I
(PD)		 DP Alt mode Switch Control Pin. In GPIO mode, this pin will enable or disable DisplayPort functionality. Otherwise DisplayPort functionality is enabled and disabled through I2C registers.
L = DisplayPort Disabled.
H = DisplayPort Enabled.
In I2C Mode, this pin is not used by TUSB1044.
24 AUXp I/O,
CMOS		 AUXp. DisplayPort AUX positive I/O connected to the DisplayPort source or sink through an AC coupling capacitor. In addition to AC coupling capacitor, this pin also requires a 100-kΩ resistor to GND between the AC coupling capacitor and the AUXp pin if the TUSB1044 is used on the DisplayPort source side, or a 1-MΩ resistor to DP_PWR (3.3V) between the AC coupling capacitor and the AUXp pin if TUSB1044 is used on the DisplayPort sink side. This pin along with AUXn is used by the TUSB1044 for AUX snooping and is routed to SBU1/2 based on the orientation of the Type-C plug.
25 AUXn I/O,
CMOS		 AUXn. DisplayPort AUX I/O connected to the DisplayPort source or sink through an AC coupling capacitor. In addition to AC coupling capacitor, this pin also requires a 100-kΩ resistor to DP_PWR (3.3V) between the AC coupling capacitor and the AUXn pin if the TUSB1044 is used on the DisplayPort source side, or a 1-MΩ resistor to GND between the AC coupling capacitor and the AUXn pin if TUSB1044 is used on the DisplayPort sink side. This pin along with AUXp is used by the TUSB1044 for AUX snooping and is routed to SBU1/2 based on the orientation of the Type-C plug.
26 SBU2 I/O,
CMOS		 SBU2. When the TUSB1044 is used on the DisplayPort source side, this pin should be DC coupled to the SBU2 pin of the Type-C receptacle. When the TUSB1044 is used on the DisplayPort sink side, this pin should be DC coupled to the SBU1 pin of the Type-C receptacle. A 2-MΩ resistor to GND is also recommended.
27 SBU1 I/O,
CMOS		 SBU1. When the TTUSB1044 is used on the DisplayPort source side, this pin should be DC coupled to the SBU1 pin of the Type-C receptacle. When the TUSB1044 is used on the DisplayPort sink side, this pin should be DC coupled to the SBU2 pin of the Type-C receptacle. A 2-MΩ resistor to GND is also recommended.
28 VCC P 3.3V Power Supply
29 DEQ1 4 Level I This pin along with DEQ0 sets the high-frequency equalizer gain for downstream facing DRX1, DRX2, DTX1, DTX2 receivers.
30 DRX1p Diff I/O Differential positive input/output for downstream facing RX1 port.
31 DRX1n Diff I/O Differential negative input/output for downstream facing RX1 port.
32 HPDIN 2 Level I
(PD)		 This pin is an input for Hot Plug Detect received from DisplayPort sink. When HPDIN is low for greater than 2ms, all DisplayPort lanes are disabled and AUX to SBU switch will remain closed. When HPDIN is high, the enabled DisplayPort lanes from AUX snoop or registers will be active.
33 DTX1p Diff I/O Differential positive input/output for downstream facing TX1 port.
34 DTX1n Diff I/O Differential negative input/output for downstream facing TX1 port.
35 UEQ0/A0 4 Level I This pin along with UEQ1 sets the high-frequency equalizer gain for upstream facing URX1, URX2, UTX1, UTX2 receivers. In I2C mode, this pin will also set TUSB1044 I2C address. Refer to Table 6-9.
36 DTX2n Diff I/O Differential negative input/output for downstream facing TX2 port.
37 DTX2p Diff I/O Differential positive input/output for downstream facing TX2 port.
38 DEQ0 4 Level I This pin along with DEQ1 sets the high-frequency equalizer gain for downstream facing URX1, URX2, UTX1, UTX2 receivers.
39 DRX2n Diff I/O Differential negative input/output for downstream facing RX2 port.
40 DRX2p Diff I/O Differential positive input/output for downstream facing RX2 port.
Thermal Pad GND Ground