JAJSG28F august   2018  – august 2020 TPS2120 , TPS2121

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
    1.     8
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Input Settling Time and Output Soft Start Control (SS)
        1. 9.3.1.1 Slew Rate vs. CSS Capacitor
      2. 9.3.2 Active Current Limiting (ILM)
      3. 9.3.3 Short-Circuit Protection
      4. 9.3.4 Thermal Protection (TSD)
      5. 9.3.5 Overvoltage Protection (OVx)
      6. 9.3.6 Fast Reverse Current Blocking (RCB)
      7. 9.3.7 Output Voltage Dip and Fast Switchover Control (TPS2121 only)
      8. 9.3.8 Input Voltage Comparator (VCOMP)
    4. 9.4 TPS2120 Device Functional Modes
    5. 9.5 TPS2121 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Manual Switchover Schematic
      2. 10.2.2 Design Requirements
      3. 10.2.3 Detailed Design Description
      4. 10.2.4 Design Procedure
        1. 10.2.4.1 Selecting PR1 and CP2 Resistors
        2. 10.2.4.2 Selecting OVx Resistors
        3. 10.2.4.3 Selecting Soft-Start Capacitor and Current Limit Resistors
      5. 10.2.5 Application Curves
    3. 10.3 Automatic Switchover with Priority (XCOMP)
      1. 10.3.1 Application Schematic
      2. 10.3.2 Design Requirements
      3. 10.3.3 Detailed Design Description
      4. 10.3.4 Design Procedure
        1. 10.3.4.1 Selecting PR1 and CP2 Resistors
      5. 10.3.5 Application Curves
    4. 10.4 Automatic Seamless Switchover with Priority (XREF)
      1. 10.4.1 Application Schematic
      2. 10.4.2 Design Requirements
      3. 10.4.3 Detailed Design Description
      4. 10.4.4 Application Curves
    5. 10.5 Highest Voltage Operation (VCOMP)
      1. 10.5.1 Application Schematic
      2. 10.5.2 Design Requirements
      3. 10.5.3 Detailed Design Description
      4. 10.5.4 Detailed Design Procedure
      5. 10.5.5 Application Curves
    6. 10.6 Reverse Polarity Protection with TPS212x
    7. 10.7 Hotplugging with TPS212x
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Links
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  15. 14Mechanical, Packaging, and Orderable Information

9.5 TPS2121 Device Functional Modes

Table 9-3 shows the TPS2121 functional behavior.

Table 9-3 TPS2121 Output Source Selection Table
DEVICE INPUTS DEVICE OUTPUTS MODE OF OPERATION
IN1 ≤ UV OR
OV1 ≥ VREF		 IN2 ≤ UV OR
OV2 ≥ VREF		 CP2 ≥
VREF		 PR1 ≥
VREF		 VCOMP XCOMP OUT ST MODE
0 X 0 0 IN2 < IN1 X IN1 H VCOMP
X 0 0 0 IN2 ≥ IN1 X IN2 L VCOMP
0 X 0 1 X X IN1 H VREF
X 0 1 0 X X IN2 L VREF
0 X 1 1 X PR1 > CP2 IN1 H XCOMP / XREF
X 0 1 1 X PR1 ≤ CP2 IN2 L XCOMP / XREF
0 1 X X X X IN1 H Invalid Input
1 0 X X X X IN2 L Invalid Input
1 1 X X X X Hi-Z H Invalid Inputs

A summary of the operation of the TPS2121 device can be found below:

  • If only one input voltage is valid (above UV and below OV) then that input will power the output.
  • If both inputs are not valid, then the output is Hi-Z.
  • ST is pulled high when the output is Hi-Z or IN1. It is pulled low when IN2 is powering the output.
  • If CP2 is pulled low, then the TPS2121 ignores this pin.
  • When CP2 is pulled high, this enables fast switchover and is compared to PR1. If PR1 > CP2 then IN1 is used, and if PR1 < CP2 then IN2 is used.
  • If both inputs are valid, CP2 is low, and PR1 is pulled high, (higher than VREF, 1.06-V typical), then IN1 is used.
  • If both inputs are valid, CP2 is low, and PR1 is pulled low, then the highest voltage input is used.