JAJSHF0B February 2019 – November 2019 BQ25887
PRODUCTION DATA.
REG06 is shown in Figure 30 and described in Table 14.
Return to Summary Table.
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Field | Reserved | AUTO_INDET_EN | TREG[1:0] | EN_CHG | CELLLOWV | VRECHG[1:0] |
Bit | Field | Type | Reset by REG_RST | Reset by WATCHDOG | Description | |
---|---|---|---|---|---|---|
7 | Reserved | R/W | Yes | Yes | Reserved bit always reads 0. | |
6 | AUTO_INDET_EN | R/W | Yes | Yes | Automatic PSEL Detection Enable:
0 – Disable PSELL detection when VBUS plugs in 1 – Enable PSEL detection when VBUS plugs in (default) |
|
5 | TREG[1] | R/W | Yes | Yes | Thermal Regulation Threshold
00 – 60°C 01 – 80°C 10 – 100°C 11 – 120°C (Default) |
|
4 | TREG[0] | R/W | Yes | Yes | ||
3 | EN_CHG | R/W | Yes | Yes | Charger Enable Configuration
0 – Charge Disable 1 – Charge Enable (default) Note: If EN_OTG and EN_CHG are set simultaneously, EN_CHG takes priority |
|
2 | CELLLOWV | R/W | Yes | Yes | Battery precharge to fast-charge threshold:
0 – 2.8 V 1 – 3.0 V (default) |
|
1 | VCELL_RECHG[1] | R/W | Yes | No | 100 mV | Cell Recharge Threshold Offset (below VCELLREG)
Offset: 50 mV Range: 50 mV – 200 mV Default: 100 mV |
0 | VCELL_RECHG[0] | R/W | Yes | No | 50 mV |