JAJSHF0B February 2019 – November 2019 BQ25887
PRODUCTION DATA.
REG12 is shown in Figure 42 and described in Table 26.
Return to Summary Table.
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 |
Field | ADC_DONE_MASK | IINDPM_MASK | VINDPM_MASK | TREG_MASK | WD_MASK | RESERVED | RESERVED | CHRG_MASK |
Bit | Field | Type | Reset by REG_RST | Reset by WATCHDOG | Description | |
---|---|---|---|---|---|---|
7 | ADC_DONE_MASK | R/W | Yes | No | ADC Conversion INT Mask Flag (only one-shot mode)
0 – ADC_DONE does produce INT pulse 1 – ADC_DONE does produce not INT pulseReserved bit always reads 0 |
|
6 | IINDPM_MASK | R/W | Yes | No | IINDPM Regulation INT Mask
0 – IINDPM entry produces INT pulse 1 – IINDPM entry does not produce INT pulse |
|
5 | VINDPM_MASK | R/W | Yes | No | VINDPM Regulation INT Mask
0 – VINDPM entry produces INT pulse 1 – VINDPM entry not produce INT pulse |
|
4 | TREG_MASK | R/W | Yes | No | IC Temperature Regulation INT Mask
0 – TREG entry produces INT pulse 1 – TREG entry produce INT pulse |
|
3 | WD_MASK | R/W | Yes | No | I2C Watchdog Timer INT Mask
0 – WD_STAT rising edge produces INT pulse 1 – WD_STAT rising edge does not produce INT |
|
2 | RESERVED | R | Yes | No | Reserved bit always reads 0h | |
1 | RESERVED | R | Yes | No | Reserved bit always reads 0h | |
0 | CHRG_MASK | R/W | Yes | No | Charge Status INT Mask
0 – CHRG_STAT[2:0] bit change produces INT 1 – CHRG_STAT[2:0] bit change does not produce INT pulse |